Abstract: A gas is ionized into a plasma. A compound of a dopant is mixed into the plasma, forming a mixed plasma. Using a semiconductor device fabrication system, a layer of III-V material is exposed to the mixed plasma to dope the layer with the dopant up to a depth in the layer, forming a shallow doped portion of the layer. The depth of the dopant is controlled by a second layer of the dopant formed at the shallow doped portion of the layer. The second layer is exposed to a solution, where the solution is prepared to erode the dopant in the second layer at a first rate. After an elapsed period, the solution is removed from the second layer, wherein the elapsed period is insufficient to erode a total depth of the layer and the shallow doped portion by more than a tolerance erosion amount.

Abstract: An OLED display includes: a first pixel including a first pixel electrode of a pixel electrode, a second pixel including a second pixel electrode of the pixel electrode, and a third pixel including a third pixel electrode of the pixel electrode; a resonance assistance layer on the first pixel electrode; an organic emission layer including a first organic emission layer on the resonance assistance layer and the second pixel electrode, a second organic emission layer on the first organic emission layer, and a third organic emission layer on the third pixel electrode; a common electrode on the organic emission layer; and a color mixture preventing layer on the common electrode and configured to absorb overlapped light in an overlapped wavelength region of a wavelength region of first light emitted by the first organic emission layer and a wavelength region of second light emitted by the second organic emission layer.

Abstract: A semiconductor light-emitting device having a longitudinal direction, and able to smoothly incline luminance for the longitudinal direction is provided. The semiconductor light-emitting device comprises a substrate and a plurality of semiconductor light-emitting layers of a predetermined shape disposed in a row on the substrate. The semiconductor light-emitting layers have such a structure that light emission amount of light-emitting surface of each semiconductor light-emitting layer inclines from a side of one predetermined end toward a side of the other end for the direction of the row.

Abstract: A light emitting device that is capable of achieving excellent color rendering property is provided. The light emitting device contains a light emitting element having a light emission peak wavelength within a range of 430 nm or more and 470 nm or less, and a fluorescent member. The fluorescent member contains a first fluorescent material that contains an Eu-activated alkaline earth aluminate, a second fluorescent material that contains a Mn-activated fluorogermanate, a third fluorescent material that contains a Ce-activated rare earth aluminate, and a fourth fluorescent material that contains an Eu-activated silicon nitride having Al and at least one of Sr and Ca.

Abstract: An imaging system may include an image sensor die, which may be backside illuminated (BSI). A light shielding layer and a conductive layer may be formed in the image sensor die. First and second portions of the conductive layer may be electrically isolated, so that the second conductive portion may be coupled to other power supply signals through a bond pad region, while the light shield may be shorted to ground. Optionally, the first and second portions may both be coupled to ground. The light shield may also be shorted through the bond pad region in a continuous conductive layer. A through oxide via may be formed in the image sensor die to couple metal interconnect structures to the conductive layer. Color filter containment structures may be formed over active image sensor pixels on the image sensor die, which may be selectively etched to improve planarity.

Abstract: Methods of forming thin-film structures including one or more NbMC layers, and structures and devices including the one or more NbMC layers are disclosed. The NbMC layers enable tuning of various structure and device properties, including resistivity, current leakage, and work function.

Abstract: An ESD protection device includes a substrate having an active fin extending in a first direction, a plurality of gate structures extending in a second direction at a given angle with respect to the first direction and partially covering the active fin, an epitaxial layer in a recess on a portion of the active fin between the gate structures, an impurity region under the epitaxial layer, and a contact plug contacting the epitaxial layer. A central portion of the impurity region is thicker than an edge portion of the impurity region, in the first direction. The contact plug lies over the central portion of the impurity region.

Abstract: Techniques are disclosed for incorporating high mobility strained channels into fin-based NMOS transistors (e.g., FinFETs such as double-gate, trigate, etc), wherein a stress material is cladded onto the channel area of the fin. In one example embodiment, a germanium or silicon germanium film is cladded onto silicon fins in order to provide a desired tensile strain in the core of the fin, although other fin and cladding materials can be used. The techniques are compatible with typical process flows, and cladding deposition can occur at a plurality of locations within typical process flow. In various embodiments, fins may be formed with a minimum width (or later thinned) so as to improve transistor performance. In some embodiments, a thinned fin also increases tensile strain across the core of a cladded fin. In some cases, strain in the core may be further enhanced by adding an embedded silicon epitaxial source and drain.

Abstract: The present technology relates to a solid-state image sensor, an imaging device, and electronic equipment configured such that an FD is shared by a plurality of pixels to further miniaturize the pixels at low cost without lowering of sensitivity and a conversion efficiency. In a configuration in which a plurality of pixels are arranged with respect to at least either of one of the OCCFs or one of the OCLs, a floating diffusion (FD) is shared by a sharing unit including a plurality of pixels, the plurality of pixels including pixels of at least either of different OCCFs or different OCLs. The present technology is applicable to a CMOS image sensor.

Abstract: The present technology relates to a solid-state image sensor, an imaging device, and electronic equipment configured such that an FD is shared by a plurality of pixels to further miniaturize the pixels at low cost without lowering of sensitivity and a conversion efficiency. In a configuration in which a plurality of pixels are arranged with respect to at least either of one of the OCCFs or one of the OCLs, a floating diffusion (FD) is shared by a sharing unit including a plurality of pixels, the plurality of pixels including pixels of at least either of different OCCFs or different OCLs. The present technology is applicable to a CMOS image sensor.

Abstract: A semiconductor device having a low feedback capacitance and a low switching loss. The semiconductor device includes: a substrate; a drift layer formed on a surface of the semiconductor substrate; a plurality of first well regions formed on a surface of the drift layer; a source region which is an area formed on a surface of each of the first well regions and defining, as a channel region, the surface of each of the first well regions interposed between the area and the drift layer; a gate electrode formed over the channel region and the drift layer thereacross through a gate insulating film; and second well regions buried inside the drift layer below the gate electrode and formed to be individually connected to each of the first well regions adjacent to one another.

Abstract: Methods of MOL S/D contact patterning of RMG devices without gouging of the Rx area or replacement of the dielectric are provided. Embodiments include forming a SOG layer around a RMG structure, the RMG structure having a contact etch stop layer and a gate cap layer; forming a lithography stack over the SOG and gate cap layers; patterning first and second TS openings through the lithography stack down to the SOG layer; removing a portion of the SOG layer through the first and second TS openings, the removing selective to the contact etch stop layer; converting the SOG layer to a SiO2 layer; forming a metal layer over the SiO2 layer; and planarizing the metal and SiO2 layers down to the gate cap layer.

Abstract: An LED module according to the present invention includes: a mounting substrate; a first LED group including a plurality of LEDs mounted in a first light-emitting area extending in a first direction on the mounting substrate; a second LED group including a plurality of LEDs mounted in a second light-emitting area located outside the first light-emitting area; a dam material surrounding a periphery of the second light-emitting area; a first fluorescent resin coating the first LED group and causing the first light-emitting area to emit light having a first color temperature; and a second fluorescent resin coating at least the second LED group and causing the second light-emitting area to emit light having a second color temperature higher than the first color temperature, and viscosity of the first fluorescent resin is higher than viscosity of the second fluorescent resin.

Abstract: Provided are a thin film transistor (TFT) substrate and a method of manufacturing the same. A TFT substrate includes: a substrate defining a pixel area, a first TFT including: an oxide semiconductor layer, a first gate electrode on the oxide semiconductor layer, a first source electrode, and a first drain electrode, a second TFT including: a second gate electrode, a polycrystalline semiconductor layer on the second gate electrode, a second source electrode, and a second drain electrode, a first gate insulating layer under the first gate electrode and the second gate electrode, the first gate insulating layer covering the oxide semiconductor layer, a second gate insulating layer under the polycrystalline semiconductor layer, the second gate insulating layer covering the first gate electrode and the second gate electrode, and an intermediate insulating layer on the first gate electrode and the polycrystalline semiconductor layer, the intermediate insulating layer including a nitride layer.

Abstract: According to an embodiment, a semiconductor memory device comprises: control gate electrodes stacked above a substrate; a semiconductor layer that extends in a first direction above the substrate and faces the control gate electrodes; and a gate insulating layer provided between these control gate electrode and semiconductor layer. The gate insulating layer comprises: a first insulating layer covering a side surface of the semiconductor layer; a charge accumulation layer covering a side surface of this first insulating layer; and a second insulating layer including a metal oxide and covering a side surface of this charge accumulation layer. The charge accumulation layer has: a first portion facing the control gate electrode; and a second portion facing a region between control gate electrodes adjacent in the first direction and including more oxygen than the first portion.

Abstract: An organic light emitting display device including a substrate, a first semiconductor element, a first lower electrode, a protection member, a first light emitting layer, a second lower electrode, and a second light emitting layer. The substrate has a first pixel region in which a light is emitted in a first direction, and a second pixel region in which a light is emitted in a second direction that is opposite to the first direction.

Abstract: To improve reliability of a semiconductor device, in a method of manufacturing the semiconductor device, a semiconductor substrate having an insulating film in which an opening that exposes each of a plurality of electrode pads is formed is provided, and a flux member including conductive particles is arranged over each of the electrode pads. Thereafter, a solder ball is arranged over each of the electrode pads via the flux member, and is then heated via the flux member so that the solder ball is bonded to each of the electrode pads. The width of the opening of the insulating film is smaller than the width (diameter) of the solder ball.

Abstract: Methods for forming an efficient and effective crossed-fins FinFET device for sensing and measuring magnetic fields and resulting devices are disclosed. Embodiments include forming first-fins, parallel to and spaced from each other, in a first direction on a substrate; forming second-fins, parallel to and spaced from each other on the substrate, in a same plane as the first fins and in a second direction perpendicular to and crossing the first-fins; forming a dummy gate with a spacer on each side over channel areas of the first and second fins; forming source/drain (S/D) regions at opposite ends of each first and second fin; forming an ILD over the fins and the dummy gate and planarizing to reveal the dummy gate; removing the dummy gate, forming a cavity; and forming a high-k/metal gate in the cavity.

Abstract: The present invention relates to a junction field effect transistor. The junction field effect transistor comprises a substrate (10), a buried layer in the substrate, a first well region (32) and a second well region (34) that are on the buried layer, a source lead-out region (50), a drain lead-out region (60), and a first gate lead-out region (42) that are in the first well region (32), and a second gate lead-out region (44) in the second well region (34). A Schottky junction interface (70) is disposed on the surface of the first well region (32). The Schottky junction interface (70) is located between the first gate lead-out region (42) and the drain lead-out region (60), and is isolated from the first gate lead-out region (42) and the drain lead-out region (60) by means of isolation structures. The present invention also relates to a manufacturing method for a junction field effect transistor.

Abstract: A solid-state light source (SSLS) with light modulation control is described. A SSLS device can include a main p-n junction region configured for recombination of electron-hole pairs for light emission. A supplementary p-n junction region is proximate the main p-n junction region to supplement the recombination of electron-hole pairs, wherein the supplementary p-n junction region has a smaller electron-hole life time than the electron-hole life time of the main p-n junction region. The main p-n junction region and the supplementary p-n junction region operate cooperatively in a light emission state and a light turn-off-state. In one embodiment, the recombination of electron-hole pairs occurs in the main p-n junction region during a light emission state, and the recombination of electron-hole pairs occurs in the supplementary p-n junction region light during the light turn off-state.