Abstract: The present technology relates to a solid-state image sensor, an imaging device, and electronic equipment configured such that an FD is shared by a plurality of pixels to further miniaturize the pixels at low cost without lowering of sensitivity and a conversion efficiency. In a configuration in which a plurality of pixels are arranged with respect to at least either of one of the OCCFs or one of the OCLs, a floating diffusion (FD) is shared by a sharing unit including a plurality of pixels, the plurality of pixels including pixels of at least either of different OCCFs or different OCLs. The present technology is applicable to a CMOS image sensor.

Abstract: An exemplary method includes forming a hard mask layer over an integrated circuit layer and implanting ions into a first portion of the hard mask layer without implanting ions into a second portion of the hard mask layer. An etching characteristic of the first portion is different than an etching characteristic of the second portion. After the implanting, the method includes annealing the hard mask layer. After the annealing, the method includes selectively etching the second portion of the hard mask layer, thereby forming an etching mask from the first portion of the hard mask layer. The method can further include using the etching mask to pattern the integrated circuit layer.

Abstract: Techniques are disclosed for fabricating a self-aligned spin-transfer torque memory (STTM) device with a dot-contacted free magnetic layer. In some embodiments, the disclosed STTM device includes a first dielectric spacer covering sidewalls of an electrically conductive hardmask layer that is patterned to provide an electronic contact for the STTM's free magnetic layer. The hardmask contact can be narrower than the free magnetic layer. The first dielectric spacer can be utilized in patterning the STTM's fixed magnetic layer. In some embodiments, the STTM further includes an optional second dielectric spacer covering sidewalls of its free magnetic layer. The second dielectric spacer can be utilized in patterning the STTM's fixed magnetic layer and may serve, at least in part, to protect the sidewalls of the free magnetic layer from redepositing of etch byproducts during such patterning, thereby preventing electrical shorting between the fixed magnetic layer and the free magnetic layer.

Abstract: A side-view type light emitting device has a bottom surface thereof as a light emission surface and a first lateral surface thereof as a mounting surface for mounting on a mounting substrate, and includes a semiconductor layered structure including a first semiconductor layer, an active layer and a second semiconductor layer; a first connecting electrode exposed from the first lateral surface and electrically connected to the first semiconductor layer; a first electrode disposed between the first semiconductor layer and the first connecting electrode; a second connecting electrode exposed from the first lateral surface; a metal wire electrically connecting an upper surface of the second semiconductor layer to the second connecting electrode; and a resin layer. In a direction perpendicular to the light emission surface, the active layer does not overlap with the first connecting electrode, and the active layer does not overlap with the second connecting electrode.

Abstract: Apparatuses relating generally to a microelectronic package having protection from electromagnetic interference are disclosed. In an apparatus thereof, a platform has an upper surface and a lower surface opposite the upper surface and has a ground plane. A microelectronic device is coupled to the upper surface of the platform. Wire bond wires are coupled to the ground plane with a pitch. The wire bond wires extend away from the upper surface of the platform with upper ends of the wire bond wires extending above an upper surface of the microelectronic device. The wire bond wires are spaced apart from one another to provide a fence-like perimeter to provide an interference shielding cage. A conductive layer is coupled to at least a subset of the upper ends of the wire bond wires for electrical conductivity to provide a conductive shielding layer to cover the interference shielding cage.

Abstract: An array substrate, a method for manufacturing the array substrate and a display device are provided. The array substrate includes a gate electrode, a gate line, a gate insulation layer, a source electrode, a drain electrode, a data line, a common electrode and a common electrode line arranged on base substrate. The common electrode line is directly connected to the common electrode.

Abstract: Provided are a thin film transistor (TFT) substrate and a method of manufacturing the same. A TFT substrate includes: a substrate defining a pixel area, a first TFT including: an oxide semiconductor layer, a first gate electrode on the oxide semiconductor layer, a first source electrode, and a first drain electrode, a second TFT including: a second gate electrode, a polycrystalline semiconductor layer on the second gate electrode, a second source electrode, and a second drain electrode, a first gate insulating layer under the first gate electrode and the second gate electrode, the first gate insulating layer covering the oxide semiconductor layer, a second gate insulating layer under the polycrystalline semiconductor layer, the second gate insulating layer covering the first gate electrode and the second gate electrode, and an intermediate insulating layer on the first gate electrode and the polycrystalline semiconductor layer, the intermediate insulating layer including a nitride layer.

Abstract: An organic light emitting display device is disclosed, which enhances an adhesion between a substrate and a routing line and minimizes a crack of the routing line. The organic light emitting display device comprises a substrate having a display area and a bending area; a routing line arranged on the bending area of the substrate; and a lower layer formed between the substrate and the routing line.

Abstract: An organic light-emitting display device and a method of manufacturing the same are disclosed and these improve electrical connection between a cathode and an auxiliary electrode in order to reduce the resistance of the cathode that covers a plurality of sub-pixels, and may prevent lateral current leakage using the same structure.

Abstract: A structure and a manufacturing method of a power semiconductor device are provided. A structure of thin semi-insulating field plates (32, 33, 34) located between metal electrodes (21, 22, 23) at the surface of the power semiconductor device is provided. The thin semi-insulating field plates (32, 33, 34) are formed by depositing before metallization and annealing after the metallization. The present invention can be used in lateral power semiconductor devices and vertical power semiconductor devices.

Abstract: An LED package is disclosed. The LED package includes: a metal reflector having a cavity formed therein; an LED chip arranged on the bottom of the cavity of the reflector; a wavelength converting panel including a lower glass plate, an upper glass plate, and a wavelength converting sheet interposed between the lower glass plate and the upper glass plate and arranged on the cavity of the reflector; and a sealing member disposed on the side surface of the lower glass plate and the side surface of the upper glass plate and connecting the wavelength converting panel to the reflector.

Abstract: A solid-state light source with built-in access resistance modulation is described. The light source can include an active region configured to emit electromagnetic radiation during operation of the light source. The active region can be formed at a p-n junction of a p-type side with a p-type contact and a n-type side with a n-type contact. The light source includes a control electrode configured to modulate an access resistance of an access region located on the p-type side and/or an access resistance of an access region located on the n-type side of the active region. The solid-state light source can be implemented in a circuit, which includes a voltage source that supplies a modulation voltage to the control electrode to modulate the access resistance(s).

Abstract: A package structure includes a redistribution layer, a chip, an encapsulant, an under bump supporting layer, an attachment layer and solder balls. The redistribution layer includes a first surface, a second surface opposite to the first surface and a patterned circuit layer disposed on the first surface, wherein an outer surface of the patterned circuit layer and the first surface are coplanar. The chip is disposed on the second surface and electrically connected to the patterned circuit layer. The encapsulant is disposed on the second surface to encapsulate the chip. The under bump supporting layer is disposed on the first surface and includes openings for exposing the outer surface. The attachment layer covers the inner surface of each opening and the exposed portion of the patterned circuit layer. The solder balls are disposed in the openings respectively and electrically connected to the patterned circuit layer.

Abstract: An electronic package structure is provided, which includes: a first carrier having an opening; at least a first electronic component and a plurality of conductive elements disposed on the first carrier; a second carrier bonded to the conductive elements; at least a second electronic component disposed on the second carrier and received in the opening of the first carrier; and an encapsulant formed on the first carrier and the second carrier and encapsulating the first electronic component, the second electronic component and the conductive elements. By receiving the second electronic component in the opening of the first carrier, the present disclosure reduces the height of the electronic package structure. The present disclosure further provides a method for fabricating the electronic package structure.

Abstract: A method for fabricating a CMOS integrated circuit structure and the CMOS integrated circuit structure. The method includes creating one or more n-type wells, creating one or more p-type wells, creating one or more pFET source-drains embedded in each of the one or more n-type wells, creating one or more nFET source-drains embedded in each of the one or more p-type wells, creating a pFET contact overlaying each of the one or more pFET source-drains, and creating an nFET contact overlaying each of the one or more nFET source-drains. A material of each of the one or more pFET source-drains includes silicon doped with a p-type material; a material of each of the one or more nFET source-drains includes silicon doped with an n-type material; a material of each pFET contact includes nickel silicide; and a material of each nFET contact comprises titanium silicide.

Abstract: A three-dimensional nonvolatile memory device and a method for fabricating the same include a semiconductor substrate, a plurality of active pillars, a plurality of gate electrodes, and a plurality of supporters. The semiconductor substrate includes a memory cell region and a contact region. The active pillars extend in the memory cell region perpendicularly to the semiconductor substrate. The gate electrodes intersect the active pillars, extend from the memory cell region to the contact region and are stacked on the semiconductor substrate. The supporters extend in the contact region perpendicularly to the semiconductor substrate to penetrate at least one or more of the gate electrodes.

Abstract: A method of making a semiconductor device including forming a first blanket layer on a substrate; forming a second blanket layer on the first blanket layer; patterning a first fin of a first transistor region and a second fin of a second transistor region in the first blanket layer and the second blanket layer; depositing a mask on the second transistor region; removing the first fin to form a trench; growing a first semiconductor layer in the trench where the first fin was removed; and growing a second semiconductor layer on the first semiconductor layer.

Abstract: To pattern a gate electrode, a mandrel of material is initially deposited and then patterned. In an embodiment the patterning is performed by performing a first etching process and to obtain a rough target and then to perform a second etching process with different etch parameters to obtain a precise target. The mandrel is then used to form spacers which can then be used to form masks to pattern the gate electrode.

Abstract: A device includes a redistribution line, and a polymer region molded over the redistribution line. The polymer region includes a first flat top surface. A conductive region is disposed in the polymer region and electrically coupled to the redistribution line. The conductive region includes a second flat top surface not higher than the first flat top surface.

Abstract: A display apparatus includes a substrate including a display region and a non-display region, a blue sub-pixel in the display region of the substrate, an imaginary line extending across the blue sub-pixel, a first sub-unit on a first side of the imaginary line, the first sub-unit including a red sub-pixel, a green sub-pixel, and a white sub-pixel, and a second sub-unit on a second side of the imaginary line, the second sub-unit including a red sub-pixel, a green sub-pixel, and a white sub-pixel, wherein the first sub-unit and the blue sub-pixel constitute a first pixel, and the second sub-unit and the blue sub-pixel constitute a second pixel, and wherein the blue sub-pixel emits light according to a data signal generated based on blue-related data of first pixel data corresponding to the first pixel and blue-related data of second pixel data corresponding to the second pixel.