Abstract: Vision correction and tracking systems may be used in laser machining systems and methods to improve the accuracy of the machining. The laser machining systems and methods may be used to scribe one or more lines in large flat workpieces such as solar panels. In particular, laser machining systems and methods may be used to scribe lines in thin film photovoltaic (PV) solar panels with accuracy, high speed and reduced cost. The vision correction and/or tracking systems may be used to provide scribe line alignment and uniformity based on detected parameters of the scribe lines and/or changes in the workpiece.

Abstract: A method of forming a film on a substrate having silicon surfaces and dielectric surfaces includes precleaning the substrate; applying an inhibitor species to the dielectric surfaces; and exposing the substrate to a precursor while maintaining a temperature of less than about 600 degrees Celsius.

Abstract: A dielectric layer (2) is arranged on the main surface (10) of a semiconductor substrate (1), and a passivation layer (6) is arranged on the dielectric layer. A metal layer (3) is embedded in the dielectric layer above an opening (12) in the substrate, and a metallization (14) is arranged in the opening. The metallization contacts the metal layer and forms a through-substrate via to a rear surface (11) of the substrate. A layer or layer sequence (7, 8, 9) comprising at least one further layer is arranged on the passivation layer above the opening. In this way the bottom of the through-substrate via is stabilized. A plug (17) may additionally be arranged in the opening without filling the opening.

Abstract: An organic light emitting display includes: an organic light emitting display panel including a light emitting surface and a non-light emitting surface opposite the light emitting surface; a heat radiation layer on the non-light emitting surface and having an emissivity equal to or greater than about 0.8 and less than about 1; and a protective member spaced from the heat radiation layer such that an air layer is between the protective member and the heat radiation layer. The protective member includes a base layer and a heat absorbing layer having an emissivity greater than an emissivity of the base layer.

Abstract: An organic light-emitting component is specified, comprising a translucent substrate (1), on which a translucent electrode (3) is arranged, comprising on the translucent electrode (3) an organic functional layer stack comprising organic functional layers having at least one organic light-emitting layer (5) and comprising a further electrode (7), wherein the at least one organic light-emitting layer (5) comprises emitter molecules having an anisotropic molecular structure which are oriented anisotropically, and wherein all the organic light-emitting layers (5, 51, 52, 53) of the organic light-emitting component are at a distance of greater than or equal to 20 nm and less than or equal to 100 nm from the further electrode (7).

Abstract: A method of making a semiconductor device including forming a first blanket layer on a substrate; forming a second blanket layer on the first blanket layer; patterning a first fin of a first transistor region and a second fin of a second transistor region in the first blanket layer and the second blanket layer; depositing a mask on the second transistor region; removing the first fin to form a trench; growing a first semiconductor layer in the trench where the first fin was removed; and growing a second semiconductor layer on the first semiconductor layer.

Abstract: A display device including a wide display region in which a seam is less likely to be noticed is provided. The display device includes two display panels that overlap with each other. An upper display panel includes a first display region and a region that transmits visible light. A lower display panel includes a second display region and a region that blocks visible light. The second display region overlaps with, on a display surface side, the region that transmits visible light. The region that blocks visible light overlaps with the first display region. At least part of an insulating layer included in the upper display panel is provided in the first display region and not provided in the region that transmits visible light.

Abstract: An electronic package apparatus is formed from a semiconductor substrate having a cavity formed therein. The cavity has a top surface, a bottom surface and a sidewall surface, and a spacer extending from the bottom surface to the top surface. The spacer is formed from a dielectric material and has at least one lateral dimension less than 0.1 cm.

Abstract: An organic light-emitting diode (OLED) display is disclosed. In one aspect, the OLED display includes a substrate, an interlayer insulating layer arranged over the substrate and an OLED arranged over the interlayer insulating layer. The OLED display also includes a source electrode and a drain electrode arranged over the interlayer insulating layer and a via layer arranged over the interlayer insulating layer and having a via hole exposing the source electrode or the drain electrode. The interlayer insulating layer includes a projecting portion which projects toward the OLED in the via hole.

Abstract: A method for fabricating a semiconductor substrate is disclosed, which includes: forming a first dielectric layer on a substrate body; foil ling a plurality of first vias penetrating the first dielectric layer to expose portions of the substrate body; forming a second dielectric layer on the first dielectric layer and the exposed portions of the substrate body, wherein the second dielectric layer extends on walls of the first vias; etching the second dielectric layer to form a plurality of openings communicating with the first vias and form a plurality of second vias penetrating the second dielectric layer in the first vias so as to expose portions of the substrate body, leaving the second dielectric layer on the walls of the first vias; and forming a circuit layer in the openings, and forming a plurality of conductive vias in the second vias for electrically connecting the circuit layer and the substrate body.

Abstract: Techniques for dielectric isolation in bulk nanosheet devices are provided. In one aspect, a method of forming a nanosheet device structure with dielectric isolation includes the steps of: optionally implanting at least one dopant into a top portion of a bulk semiconductor wafer, wherein the at least one dopant is configured to increase an oxidation rate of the top portion of the bulk semiconductor wafer; forming a plurality of nanosheets as a stack on the bulk semiconductor wafer; patterning the nanosheets to form one or more nanowire stacks and one or more trenches between the nanowire stacks; forming spacers covering sidewalls of the nanowire stacks; and oxidizing the top portion of the bulk semiconductor wafer through the trenches, wherein the oxidizing step forms a dielectric isolation region in the top portion of the bulk semiconductor wafer. A nanowire FET and method for formation thereof are also provided.

Abstract: A method of forming a space includes a step of tenting, on a substrate having a recessed portion, a dry film including a dry film material that is to be a top plate on the recessed portion. The step of tenting the dry film includes a press period and a release period and performs a press-release cycle of the press period and the release period a plurality of times, a pressed state in which the dry film is pressed against the substrate by using a pressing member is maintained during the press period, and a released state in which the pressed state is released is maintained during the release period.

Abstract: A semiconductor device includes an n+ type silicon carbide substrate, an n? type layer, an n type layer, a plurality of trenches, a p type region, an n+ type region, a gate insulating film, a gate electrode, a source electrode, a drain electrode, and a channel. The plurality of trenches is disposed in a planar matrix shape. The n+ type region is disposed in a planar mesh type with openings, surrounds each of the trenches, and is in contact with the source electrode between the trenches adjacent to each other in a planar diagonal direction. The p type region is disposed in the opening of the n+ type region in a planar mesh type.

Abstract: In some embodiments, a semiconductor structure includes a first device and a second device. The first device has a first surface. The first device includes a first active region defined by a first material system. The second device has a second surface. The second surface is coplanar with the first surface. The second device includes a second active region defined by a second material system. The second material system is different from the first material system.

Abstract: Techniques for dielectric isolation in bulk nanosheet devices are provided. In one aspect, a method of forming a nanosheet device structure with dielectric isolation includes the steps of: optionally implanting at least one dopant into a top portion of a bulk semiconductor wafer, wherein the at least one dopant is configured to increase an oxidation rate of the top portion of the bulk semiconductor wafer; forming a plurality of nanosheets as a stack on the bulk semiconductor wafer; patterning the nanosheets to form one or more nanowire stacks and one or more trenches between the nanowire stacks; forming spacers covering sidewalls of the nanowire stacks; and oxidizing the top portion of the bulk semiconductor wafer through the trenches, wherein the oxidizing step forms a dielectric isolation region in the top portion of the bulk semiconductor wafer. A nanowire FET and method for formation thereof are also provided.

Abstract: An enhancement-mode GaN transistor with reduced gate leakage current between a gate contact and a 2DEG region and a method for manufacturing the same. The enhancement-mode GaN transistor including a GaN layer, a barrier layer disposed on the GaN layer with a 2DEG region formed at an interface between the GaN layer and the barrier layer, and source contact and drain contacts disposed on the barrier layer. The GaN transistor further includes a p-type gate material formed above the barrier layer and between the source and drain contacts and a gate metal disposed on the p-type gate material, with wherein the p-type gate material including comprises a pair of self-aligned ledges that extend toward the source contact and drain contact, respectively.

Abstract: Semiconductor devices include a semiconductor substrate containing a source region and a drain region, a gate structure supported by the semiconductor substrate between the source region and the drain region, a composite drift region in the semiconductor substrate, the composite drift region extending laterally from the drain region to at least an edge of the gate structure, the composite drift region including dopant having a first conductivity type, wherein at least a portion of the dopant is buried beneath the drain region at a depth exceeding an ion implantation range, and a well region in the semiconductor substrate. The well region has a second conductivity type and is configured to form a channel therein under the gate structure during operation. Methods for the fabrication of semiconductor devices are described.

Abstract: A semiconductor device includes a first transistor, a second transistor and a third transistor provided on a substrate, the first to third transistors respectively including source and drain regions spaced apart from each other, a gate structure extending in a first direction on the substrate and interposed between the source and drain regions, and a channel region connecting the source and drain regions to each other. A channel region of the second transistor and a channel region of the third transistor respectively include a plurality of channel portions, the plurality of channel portions spaced apart from each other in a second direction, perpendicular to an upper surface of the substrate, and connected to the source and drain regions, respectively. A width of a channel portion of the third transistor in the first direction is greater than a width of a channel portion of the second transistor in the first direction.

Abstract: A light-bar structure includes a first substrate, a second substrate, and an insulation layer. The first substrate includes a first anode region and a plurality of element regions. Each of the element regions is configured to allow a light-emitting element to be disposed on. At least one of the element regions includes an anode portion and a node portion. The anode portion is connected to the first anode region. The second substrate includes a grounding region and a second anode region. The anode portion is disposed correspondingly to the grounding region. The node portion is disposed correspondingly to the second anode region. The insulation layer is disposed between the first substrate and the second substrate.

Abstract: A backplate having a folding region and an unfolding region adjacent to the folding region includes: first and second material layers corresponding to the folding and unfolding regions; and a third material layer between the first and second material layers, the third material layer is more rigid than the first and second materials layers, wherein the first and second material layers extend from the folding region to the unfolding regions such that a thickness of the first and second material layers is gradually reduced from the folding region to the unfolding region.