Abstract: A variable resistance memory device includes vertical electrodes vertically projecting from a substrate, first horizontal electrodes stacked along the vertical electrodes, second horizontal electrodes stacked along the vertical electrodes, and a variable resistance layer interposed between the vertical electrodes and the first and second horizontal electrodes, wherein the first and second horizontal electrodes are arranged in directions crossing with each other.

Abstract: A field effect transistor device includes a fin including a semiconductor material arranged on an insulator layer, the fin including a channel region, a hardmask layer arranged partially over the channel region of the fin, a gate stack arranged over the hardmask layer and over the channel region of the fin, a metallic alloy layer arranged on a first portion of the hardmask layer, the metallic alloy layer arranged adjacent to the gate stack, and a first spacer arranged adjacent to the gate stack and over the metallic alloy layer.

Abstract: A superjunction semiconductor device is disclosed in which the trade-off relationship between breakdown voltage characteristics and voltage drop characteristics is considerably improved, and it is possible to greatly improve the charge resistance of an element peripheral portion and long-term breakdown voltage reliability. It includes parallel pn layers of n-type drift regions and p-type partition regions in superjunction structure. PN layers are depleted when off-state voltage is applied. Repeating pitch of the second parallel pn layer in a ring-like element peripheral portion encircling the element active portion is smaller than repeating pitch of the first parallel pn layer in the element active portion. Element peripheral portion includes low concentration n-type region on the surface of the second parallel pn layer. The depth of p-type partition region of an outer peripheral portion in the element peripheral portion is smaller than the depth of p-type partition region of an inner peripheral portion.

Abstract: A semiconductor device and a method for manufacturing the same are disclosed, which can improve device characteristics by increasing a process margin between an active region and a storage node contact. The semiconductor device includes an active region, a device isolation film formed to have a lower height than the active region, and exposing an upper part of the active region, and a barrier pattern formed at a sidewall of the exposed active region of an upper part of the device isolation film.

Abstract: The invention relates to a preparation process for thin semiconducting inorganic films comprising various metals (Cu/In/Zn/Ga/Sn), selenium and/or sulfur. The process uses molecular precursors comprising metal complexes with oximato ligands. Copper-based chalcopyrites of the I-III-IV2-type are prepared with high purity at low temperatures under ambient conditions. The thin films can be used in photovoltaic panels (solar cells).

Abstract: An organic light-emitting display apparatus includes: a substrate including an emission region and a non-emission region and having a recess formed in at least a portion of the non-emission region; a black matrix disposed in the recess; a thin film transistor disposed on the non-emission region of the substrate and including an active layer, a gate electrode, and source and drain electrodes; a pixel electrode disposed on the emission region of the substrate and electrically connected to one of the source and drain electrodes; an organic emission layer disposed on the pixel electrode; and an opposite electrode disposed on the organic emission layer.

Abstract: A method and apparatus are provided for treating a substrate. The substrate is positioned on a support in a thermal treatment chamber. Electromagnetic radiation is directed toward the substrate to anneal a portion of the substrate. Other electromagnetic radiation is directed toward the substrate to preheat a portion of the substrate. The preheating reduces thermal stresses at the boundary between the preheat region and the anneal region. Any number of anneal and preheat regions are contemplated, with varying shapes and temperature profiles, as needed for specific embodiments. Any convenient source of electromagnetic radiation may be used, such as lasers, heat lamps, white light lamps, or flash lamps.

Abstract: A method for fabricating a field effect transistor device includes depositing a hardmask over a semiconductor layer depositing a metallic alloy layer over the hardmask, defining a semiconductor fin, depositing a dummy gate stack material layer conformally on exposed portions of the fin, patterning a dummy gate stack by removing portions of the dummy gate stack material using an etching process that selectively removes exposed portions of the dummy gate stack without appreciably removing portions of the metallic alloy layer, removing exposed portions of the metallic alloy layer, forming spacers adjacent to the dummy gate stack, forming source and drain regions on exposed regions of the semiconductor fin, removing the dummy gate stack, removing exposed portions of the metallic alloy layer, and forming a gate stack conformally over exposed portions of the insulator layer and the semiconductor fin.

Abstract: A method for fabricating a small-scale MOS device, including: preparing a substrate; forming a first trench in the substrate along a first side of the gate region and forming a second trench in the substrate along a second side of the gate region, the first side of the gate region opposite the second side of the gate region; forming a first lightly doped drain region and a second lightly doped drain region in the first trench and the second trench, respectively; forming a third trench in the substrate overlapping at least a first portion of the first lightly doped drain region and a fourth trench in the substrate overlapping at least a first portion of the second lightly doped drain region; and forming a source region and a drain region in the third trench and the fourth trench, respectively.

Abstract: A memory cell of a nonvolatile memory and a capacitive element are formed over the same semiconductor substrate. The memory cell includes a control gate electrode formed over the semiconductor substrate via a first insulating film, a memory gate electrode formed adjacent to the control gate electrode over the semiconductor substrate via a second insulating film, and the second insulating film having therein a charge storing portion. The capacitive element includes a lower electrode formed of the same layer of a silicon film as the control gate electrode, a capacity insulating film formed of the same insulating film as the second insulating film, and an upper electrode formed of the same layer of a silicon film as the memory gate electrode. The concentration of impurities of the upper electrode is higher than that of the memory gate electrode.

Abstract: A method is provided for forming a printed top gate thin film transistor (TFT) with a short channel length. The method provides a substrate with a low surface energy top surface. A metal ink line is continuously printed across a region of the substrate top surface, and in response to the surface tension of the printed metal ink, discrete spherical ink caps are formed in the region. Then, the surface energy of the substrate top surface in the region is increased. A source metal ink line is printed overlying a source spherical ink cap contact, and a drain metal ink line, parallel to the source metal ink line, is printed overlying a drain spherical ink cap contact. After depositing a semiconductor film, a channel is formed in the semiconductor film between the source and drain spherical ink cap contacts having a channel length equal to the first distance.

Abstract: The present invention provides methods and systems for discretized, combinatorial processing of regions of a substrate such as for the discovery, implementation, optimization, and qualification of new materials, processes, and process sequence integration schemes used in integrated circuit fabrication. A substrate having an array of differentially processed regions thereon is processed by delivering materials to or modifying regions of the substrate.

Abstract: Ferroelectric capacitor structures for integrated decoupling capacitors and the like. The ferroelectric capacitor structure includes two or more ferroelectric capacitors connected in series with one another between voltage nodes. The series connection of the ferroelectric capacitors reduces the applied voltage across each, enabling the use of rough ferroelectric dielectric material, such as PZT deposited by MOCVD. Matched construction of the series-connected capacitors, as well as uniform polarity of the applied voltage across each, is beneficial in reducing the maximum voltage across any one of the capacitors, reducing the vulnerability to dielectric breakdown.

Abstract: An insulated gate bipolar transistor (IGBT) includes a first conductivity type substrate and a second conductivity type drift layer on the substrate. The second conductivity type is opposite the first conductivity type. The IGBT further includes a current suppressing layer on the drift layer. The current suppressing layer has the second conductivity type and has a doping concentration that is larger than a doping concentration of the drift layer. A first conductivity type well region is in the current suppressing layer. The well region has a junction depth that is less than a thickness of the current suppressing layer, and the current suppressing layer extends laterally beneath the well region. A second conductivity type emitter region is in the well region.

Abstract: A semiconductor integrated circuit includes a plurality of memory cells arranged in a cell-placement row extending in a first direction, a first N well and a first P well arranged in a second direction perpendicular to the first direction in each area of the memory cells, and a second N well and a second P well each having the same length as a width of the cell-placement row and situated between at least two adjacent memory cells of the plurality of memory cells, wherein the first N well and the second N well are integrated, and the first P well and the second P well are integrated.

Abstract: A combination of deposition processes can be used to evaluate layer properties using a combinatorial workflow. The processes can include a base ALD process and another process, such as a PVD process. The high productivity combinatorial technique can provide an evaluation of the material properties for given ALD base layer and PVD additional elements. An ALD process can then be developed to provide the desired layers, replacing the ALD and PVD combination.

Abstract: A semiconductor device includes a substrate, a first land formed in a first surface of the substrate, a second land formed in a second surface of the substrate, a first terminal coupled to the second land, a line coupled to the first land and the second land, a second terminal formed in the second surface of the substrate and a branch line coupled to the line and the second terminal. The second terminal is coupled to the first land and the second land and is not coupled to other lands in the first surface. The second surface is different surface from the first surface.

Abstract: The semiconductor memory device of the present invention includes a plurality of memory strings having a plurality of electrically reprogrammable memory cells connected in series, the memory strings having a column shaped semiconductor, a first insulation film formed around the column shaped semiconductor, a charge accumulation layer formed around the first insulation film, a second insulation film formed around the charge accumulation film and a plurality of electrodes formed around the second insulation film, a bit line connected to one end of the memory strings via a plurality of selection transistors, and a conducting layer extending in two dimensions and in which the plurality of electrodes of the memory strings and the plurality of electrodes of different memory strings are shared respectively, wherein each end part of the conducting layer is formed in step shapes in a direction parallel with the bit line.

Abstract: A device includes a first and a second MOS device cascaded with the first MOS device to form a first finger. A drain of the first MOS device and a source of the second MOS device are joined to form a first common source/drain region. The device further includes a third and a fourth MOS device cascaded with the third MOS device to form a second finger. A drain of the third MOS device and a source of the fourth MOS device are joined to form a second common source/drain region. The first and the second common source/drain regions are electrically disconnected from each other. Sources of the first and the third MOS devices are interconnected. Drains of the second and the fourth MOS devices are interconnected. Gates of the first and the third MOS devices are interconnected. Gates of the second and the fourth MOS devices are interconnected.

Abstract: In a method and device for machining material, an unfocused beam of laser radiation is focused and directed at the material surface, creating an interface of laser radiation and material to be machined. The beam waist, which results from the focusing the laser radiation, is held in the region of the interface of laser radiation and material. The spacing of the beam waist from the upper or lower side of the interface in the axial direction corresponds at most to triple the value of the penetration depth of the interface into the material. The focusing is effected such that components of the laser radiation are made divergent not just in the propagation direction downstream of the beam waist but also in the beam waist itself and/or also in the propagation direction upstream of the beam waist.