Abstract: A semiconductor device comprises a semiconductor substrate; a channel layer of at least one III-V semiconductor compound above the semiconductor substrate; a gate electrode above a first portion of the channel layer; a source region and a drain region above a second portion of the channel layer; and a dopant layer comprising at least one dopant contacting the second portion of the channel layer.

Abstract: A device includes a redistribution line, and a polymer region molded over the redistribution line. The polymer region includes a first flat top surface. A solder region is disposed in the polymer region and electrically coupled to the redistribution line. The solder region includes a second flat top surface not higher than the first flat top surface.

Abstract: Methods of forming a microelectronic packaging structure and associated structures formed thereby are described. Those methods may include attaching a microfluidic die to a package structure, wherein the microfluidic die comprises a plurality of asymmetric electrodes that may be coupled with signal pads disposed within the package structure.

Abstract: According to one embodiment, a nonvolatile semiconductor memory device is provided. The element isolation insulating bodies form active areas extending in one direction along a surface of a semiconductor substrate in a surface region of the semiconductor substrate, and partition the surface region into the active areas. The tunnel insulating films are formed on the active areas respectively. The floating gate electrodes are formed on the tunnel insulating films respectively. The inter-gate insulating films are formed on the floating gate electrodes. The control gate electrodes are provided on the inter-gate insulating films. The source regions and drain regions are formed in the active areas respectively. Each of the active areas has steps at side surfaces. A width of a portion of each of the active areas deeper than the steps is larger than that of a portion of each of the active areas shallower than the steps.

Abstract: An organic electroluminescent display device includes a first insulating layer that buries a peripheral portion of a first electrode and has an opening exposing an area of the first electrode inner to the peripheral portion thereof; a second electrode that is in contact with the first electrode in the opening and is provided continuously on a top surface of the first electrode and onto a top surface of the first insulating layer; a second insulating layer covering a peripheral portion of the second electrode; an organic EL layer; and a third electrode. The second electrode includes a stepped portion. An area where the stepped portion is included and the second electrode, the organic electroluminescence layer and the third electrode overlap each other is a light emitting area. Light emitted by the organic EL layer is reflected by the stepped portion.

Abstract: A semiconductor package having a lead frame over which a first device and a second device are spaced is provided. The lead frame includes a die pad upon which a first chip and a second chip are spaced and bonded. The first chip includes the first device, which has a first operating voltage. The second chip includes the second device, which has a second operating voltage greater than the first operating voltage. A dielectric layer is arranged between the die pad and the second device. A method for manufacturing the semiconductor package is also provided.

Abstract: An integrated circuit is formed on a semiconductor substrate and includes a trench conductor and a first transistor formed on the surface of the substrate. The transistor includes: a transistor gate structure, a first doped region extending in the substrate between a first edge of the gate structure and an upper edge of the trench conductor, and a first spacer formed on the first edge of the gate structure and above the first doped region. The first spacer completely covers the first doped region and a silicide is present on the trench conductor but is not present on the surface of the first doped region.

Abstract: Affixed over a transparent growth substrate (34) of an LED die (30) is a transparent rectangular pillar (40), having a footprint approximately the same size as the LED die. The pillar height is greater than a length of the LED die, and the pillar has an index (n) approximately equal to that of the substrate (e.g., 1.8), so there is virtually no TIR at the interface due to the matched indices. Surrounding the pillar and the LED die is a lens portion (42) having a diameter between 1.5-3 times the length of the LED die. The index of the lens portion is about 0.8 times the index of the substrate. The lens portion may have a dome shape (46). A large portion of the light exiting the substrate is internally reflected off the lateral pillar/cylinder interface and exits the top surface of the pillar. Thus, the emission is narrowed and light extraction efficiency is increased.

Abstract: Vision correction and tracking systems may be used in laser machining systems and methods to improve the accuracy of the machining. The laser machining systems and methods may be used to scribe one or more lines in large flat workpieces such as solar panels. In particular, laser machining systems and methods may be used to scribe lines in thin film photovoltaic (PV) solar panels with accuracy, high speed and reduced cost. The vision correction and/or tracking systems may be used to provide scribe line alignment and uniformity based on detected parameters of the scribe lines and/or changes in the workpiece.

Abstract: A method and apparatus are provided for treating a substrate. The substrate is positioned on a support in a thermal treatment chamber. Electromagnetic radiation is directed toward the substrate to anneal a portion of the substrate. Other electromagnetic radiation is directed toward the substrate to preheat a portion of the substrate. The preheating reduces thermal stresses at the boundary between the preheat region and the anneal region. Any number of anneal and preheat regions are contemplated, with varying shapes and temperature profiles, as needed for specific embodiments. Any convenient source of electromagnetic radiation may be used, such as lasers, heat lamps, white light lamps, or flash lamps.

Abstract: According to an embodiment, a non-volatile storage device includes a first layer, a second layer formed on the first layer, a stacked body including a plurality of conductive films stacked on the second layer, and a semiconductor pillar which penetrates the stacked body and the second layer and reaches the first layer. The semiconductor pillar includes a semiconductor film formed along an extending direction of the semiconductor pillar, and a memory film which covers a periphery of the semiconductor film. The memory film includes a first portion formed between the stacked body and the semiconductor film and a second portion formed between the second layer and the semiconductor film. An outer periphery of the second portion in a plane perpendicular to the extending direction is wider than an outer periphery of the first portion on a second layer side of the stacked body.

Abstract: A vertical transistor and a manufacturing method thereof are provided herein. The manufacturing method includes forming a first patterned conductive layer on a substrate; forming a patterned metal oxide layer on the first patterned conductive layer, in which the patterned metal oxide layer includes a first patterned insulator layer, a second patterned insulator layer, and a second patterned conductive layer; forming a semiconductor layer; and forming a third patterned conductive layer. The first patterned insulator layer, the second patterned insulator layer, and the second patterned conductive layer are made by using a single metal oxide material. The oxygen concentration of the second patterned conductive layer is different from the oxygen concentrations of the first patterned insulator layer and the second patterned insulator layer.

Abstract: A field effect transistor device includes a fin including a semiconductor material arranged on an insulator layer, the fin including a channel region, a hardmask layer arranged partially over the channel region of the fin, a gate stack arranged over the hardmask layer and over the channel region of the fin, a metallic alloy layer arranged on a first portion of the hardmask layer, the metallic alloy layer arranged adjacent to the gate stack, and a first spacer arranged adjacent to the gate stack and over the metallic alloy layer.

Abstract: One embodiment of the present invention is a semiconductor device which includes a gate electrode; a gate insulating film formed to cover the gate electrode; a semiconductor layer formed over the gate insulating film and placed above the gate electrode; a second insulating film formed over the semiconductor layer; a first insulating film formed over a top surface and a side surface of the second insulating film, a side surface of the semiconductor layer, and the gate insulating film; silicon layers and which are formed over the first insulating film and electrically connected to the semiconductor layer; and a source electrode and a drain electrode which are formed over the silicon layers. The source electrode and the drain electrode are electrically separated from each other over the first insulating film. The semiconductor layer is not in contact with each of the source electrode and the drain electrode.

Abstract: An electronic circuit on a strained semiconductor substrate, includes: electronic components on a first surface of a semiconductor substrate; and at least portions of a layer of a porous semiconductor material on the side of a second surface of the semiconductor substrate, opposite to the first surface, to bend the semiconductor substrate.

Abstract: A package-on-package (POP), including a semiconductor device, and a multi-chip-package located above the semiconductor device, wherein the semiconductor device includes a substrate including a first surface, a plurality of electrodes formed on the first surface, a second surface opposite to the first surface, a plurality of lands formed on the second surface, and a plurality of wirings, (a2) a semiconductor chip mounted over the first surface of the substrate, and (a3) a plurality of first solder balls formed on the lands, respectively, wherein the multi-chip-package is electrically connected with the semiconductor device via a plurality of second solder balls, wherein the plurality of second solder balls are connected with the plurality of electrodes, respectively.

Abstract: A method for fabricating a field effect transistor device includes depositing a hardmask over a semiconductor layer depositing a metallic alloy layer over the hardmask, defining a semiconductor fin, depositing a dummy gate stack material layer conformally on exposed portions of the fin, patterning a dummy gate stack by removing portions of the dummy gate stack material using an etching process that selectively removes exposed portions of the dummy gate stack without appreciably removing portions of the metallic alloy layer, removing exposed portions of the metallic alloy layer, forming spacers adjacent to the dummy gate stack, forming source and drain regions on exposed regions of the semiconductor fin, removing the dummy gate stack, removing exposed portions of the metallic alloy layer, and forming a gate stack conformally over exposed portions of the insulator layer and the semiconductor fin.

Abstract: According to one embodiment, a magnetoresistive element includes a first magnetic layer having a variable magnetization direction; a second magnetic layer having an invariable magnetization direction; and a tunnel barrier layer provided between the first magnetic layer and the second magnetic layer and including an MgFeO film, wherein the MgFeO film contains at least one element selected from a group consisting of Ti, V, Mn, and Cu.

Abstract: A field effect transistor device includes a fin including a semiconductor material arranged on an insulator layer, the fin including a channel region, a hardmask layer arranged partially over the channel region of the fin, a gate stack arranged over the hardmask layer and over the channel region of the fin, a metallic alloy layer arranged on a first portion of the hardmask layer, the metallic alloy layer arranged adjacent to the gate stack, and a first spacer arranged adjacent to the gate stack and over the metallic alloy layer.

Abstract: A method for fabricating a semiconductor device includes: forming an insulation layer over a semiconductor substrate; forming a first conductive layer over the insulation layer; forming a plurality of buried bit lines and insulation layer patterns isolated by a plurality of trenches, wherein the plurality of trenches are formed by etching the first conductive layer and the insulation layer; forming a sacrificial layer to gap-fill the trenches; forming a second conductive layer over the buried bit lines and the sacrificial layer; and forming a plurality of pillars over each of the buried bit lines by etching the second conductive layer.