Abstract: Embodiments of the present invention provide an electrically controlled optical fuse. The optical fuse is activated electronically instead of by the light source itself. An applied voltage causes the fuse temperature to rise, which induces a transformation of a phase changing material from transparent to opaque. A gettering layer absorbs excess atoms released during the transformation.

Abstract: A semiconductor device, includes: a connection member including a first pad formed on a principal surface thereof; a semiconductor chip including a circuit-formed surface on which a second pad is formed, the chip mounted on the connection member so that the circuit-formed surface faces the principal surface; and a solder bump that connects the first and second pads and is made of metal containing Bi and Sn, wherein the bump includes a first interface-layer formed adjacent to the second pad, a second interface-layer formed adjacent to the first pad, a first intermediate region formed adjacent to either one of the interface-layers, and a second intermediate region formed adjacent to the other one of the interface-layers and formed adjacent to the first intermediate region; Bi-concentration in the first intermediate region is higher than a Sn-concentration; and a Sn-concentration in the second intermediate region is higher than a Bi-concentration.

Abstract: A semiconductor device comprises a semiconductor substrate doped with dopants of a first type and a vertical transistor composed of one or more transistor cells. Each transistor cell has a first region formed in the substrate and doped with dopants of a second type, and the first regions form first pn-junctions with the surrounding substrate. At least a first well region is formed in the substrate and doped with dopants of a second type to form a second pn-junction with the substrate. The first well region is electrically connected to the first regions of the vertical transistor via a semiconductor switch. The semiconductor device comprises a detection circuit, which is integrated in the substrate and configured to detect whether the first pn-junctions are reverse biased. The switch is opened when the first pn-junctions are reverse biased and the switch is closed when the first pn-junctions are not reverse biased.

Abstract: A semiconductor device comprises semiconductor substrate including vertical transistor and with dopants of a first type. Each transistor cell of transistor has body region formed in substrate and with dopants of second type. The body regions form first pn-junctions with substrate. A first well region is formed in substrate and with dopants of a second type forming a second pn-junction with substrate. Switch connects this first well region to body regions. A second well region is formed in the substrate and with dopants of a second type to form third pn-junction with substrate. Detection circuit is integrated in the second well region and to detect whether the first pn-junctions are reverse biased. The switch connects or disconnects the first well region(s) and the body regions of the transistor cell, and is opened, when the first pn-junctions are reverse biased, and closed, when the first pn-junctions are not reverse biased.

Abstract: The semiconductor device has a barrier layer formed on a channel layer, an n type diffusion preventing layer formed on the barrier layer and containing aluminum, and a source electrode and a drain electrode formed on the diffusion preventing layer. The semiconductor device further has a p type cap layer formed on the diffusion preventing layer sandwiched between the source electrode and the drain electrode and a gate electrode formed on the cap layer. The diffusion preventing layer has an aluminum composition ratio greater than the aluminum composition ratio of the barrier layer.

Abstract: An organic light-emitting component includes a first light-emitting layer sequence, which is designed to emit light in a first wavelength range during the operation of the component. A second light-emitting layer sequence is designed to emit light in a second wavelength range during the operation of the component. A charge carrier generating layer sequence is designed to output charge carriers to the first light-emitting layer sequence and to the second light-emitting layer sequence during the operation of the component. The first wavelength range differs from the second wavelength range. The charge carrier generating layer sequence is arranged between the first light-emitting layer sequence and the second light-emitting layer sequence in a stacking direction of the organic light-emitting component.

Abstract: A semiconductor device in which a diode region and an IGBT region are formed on a same semiconductor substrate is provided. The diode region includes a plurality of first conductivity type anode layers exposed to a surface of the semiconductor substrate and separated from each other. The IGBT region includes a plurality of first conductivity type body contact layers that are exposed to the surface of the semiconductor substrate and separated from each other. The anode layer includes at least one or more of the first anode layers. The first anode layer is formed in a position in the proximity of at least IGBT region, and an area of a plane direction of the semiconductor substrate in each of the first anode layers is larger than the area of a plane direction of the semiconductor substrate in the body contact layer in the closest proximity of the diode region.

Abstract: A MTJ for a spintronic device is disclosed and includes a thin seed layer that enhances perpendicular magnetic anisotropy (PMA) in an overlying laminated layer with a (Co/X)n or (CoX)n composition where n is from 2 to 30, X is one of V, Rh, Ir, Os, Ru, Au, Cr, Mo, Cu, Ti, Re, Mg, or Si, and CoX is a disordered alloy. The seed layer is preferably NiCr, NiFeCr, Hf, or a composite thereof with a thickness from 10 to 100 Angstroms. Furthermore, a magnetic layer such as CoFeB may be formed between the laminated layer and a tunnel barrier layer to serve as a transitional layer between a (111) laminate and (100) MgO tunnel barrier. The laminated layer may be used as a reference layer, dipole layer, or free layer in a MTJ. Annealing between 300° C. and 400° C. may be used to further enhance PMA in the laminated layer.

Abstract: An optical sensor that can be produced at a low cost from inexpensive silicon fine particles as raw materials and a method for making the optical sensor are provided. In an optical sensor 1, a layer of epoxidized n-type silicon fine particles 24 coated with a coating film having a functional group is selectively fixed and bonded onto only a pattern portion of a surface of a transparent electrode 51 coated with a coating film having a first functional group, and a layer of p-type silicon fine particles 25 coated with a coating film having a third functional group is fixed and bonded thereon. The first and second functional groups and the second and third coupling groups are respectively fixed with each other via bonds formed between them and coupling reactive groups in a coupling agent.

Abstract: A silicon carbide layer includes a first region having a first conductivity type, a second region provided on the first region and having a second conductivity type, and a third region provided on the second region and having the first conductivity type. A trench having an inner surface is formed in the silicon carbide layer. The trench penetrates the second and third regions. The inner surface of the trench has a first side wall and a second side wall located deeper than the first side wall and having a portion made of the second region. Inclination of the first side wall is smaller than inclination of the second side wall.

Abstract: In a method of manufacture for a nitride semiconductor light emitting element including: a monocrystalline substrate; and an AlN layer; and a first nitride semiconductor layer of a first electrical conductivity type; and a light emitting layer made of an AlGaN-based material; and a second nitride semiconductor layer of a second electrical conductivity type, a step of forming the AlN layer includes: a first step of supplying an Al source gas and a N source gas into the reactor to generate a group of AlN crystal nuclei having Al-polarity to be a part of the AlN layer on the surface of the monocrystalline substrate; and a second step of supplying the Al source gas and the N source gas into the reactor to form the AlN layer, after the first step.

Abstract: A memory device array with spaced apart parallel isolation regions formed in a semiconductor substrate, with an active region between each pair of adjacent isolation regions. Each isolation region includes a trench formed into the substrate surface and an insulation material formed in the trench. Portions of a top surface of the insulation material are recessed below the surface of the substrate. Each active region includes a column of memory cells each having spaced apart first and second regions with a channel region therebetween, a floating gate over a first channel region portion, and a select gate over a second channel region portion. The select gates are formed as continuous word lines extending perpendicular to the isolation regions and each forming the select gates for one row of the memory cells. Portions of each word line extend down into the trenches and disposed laterally adjacent to sidewalls of the trenches.

Abstract: A non-volatile memory cell includes a p-channel non-volatile transistor having a source and a drain defining a channel and a gate overlying the channel and an n-channel non-volatile transistor having a source and a drain defining a channel and a gate overlying the channel. In at least one of the p-channel non-volatile transistor and the n-channel non-volatile transistor, a lightly-doped drain region extends from the drain into the channel.

Abstract: This application relates to a display including a first layer of material including a first aperture having at least one side, a first substrate separated from the first layer of material by a gap, where the first substrate is arranged to pass through a portion of light emitted from a light source into the gap. The display further includes a movable shutter arranged within the gap, where the shutter is movable to at least a first position and a second position, to obstruct passage of the portion of light through the first aperture at the first position. The movable shutter has a first edge, and in the first position, the movable shutter is aligned with the first aperture such that the first edge extends a first length past the at least one side of the first aperture.

Abstract: A three-dimensional nonvolatile memory device and a method for fabricating the same include a semiconductor substrate, a plurality of active pillars, a plurality of gate electrodes, and a plurality of supporters. The semiconductor substrate includes a memory cell region and a contact region. The active pillars extend in the memory cell region perpendicularly to the semiconductor substrate. The gate electrodes intersect the active pillars, extend from the memory cell region to the contact region and are stacked on the semiconductor substrate. The supporters extend in the contact region perpendicularly to the semiconductor substrate to penetrate at least one or more of the gate electrodes.

Abstract: There is provided a method for manufacturing a light emitting diode, LED, matrix (100) comprising the steps of providing with a maintained integrity a conductor sheet (150) with a plurality of component areas (111) interconnected with meandering connection tracks (116), mounting a plurality of LEDs (120) to a respective component area thereby forming a subassembly (100?), trimming and stretching the subassembly thereby straightening the connection tracks such that an m×n LED conductor matrix is formed during the step of stretching.

Abstract: This invention relates to MEMS display apparatus and methods for assembly thereof that include a plurality of light modulators having components substantially surrounded in a liquid that reduces the effects of stiction and improves the optical and electromechanical performance of the display apparatus. The invention also relates to methods for aligning components of a MEMS display to establish a correspondence between the plurality of light modulators and a plurality of apertures to regulate the transmission of light through the apparatus.

Abstract: A light emitting device includes a p-side heterostructure, an n-side heterostructure, an active region disposed between the p-side heterostructure and the n-side heterostructure. An electron blocking layer (EBL) disposed between the p-side heterostructure and the active region comprises an aluminum containing group-III-nitride alloy. An aluminum composition of the EBL decreases as a function of distance along a [0001] direction from the active region towards the p-side heterostructure over a majority of the thickness of the EBL.

Abstract: A method for forming an oxide semiconductor film having favorable semiconductor characteristics is provided. In addition, a method for manufacturing a semiconductor device having favorable electric characteristics, with use of the oxide semiconductor film is provided. A method for forming an oxide semiconductor film including the steps of forming an oxide semiconductor film, forming a hydrogen permeable film over and in contact with the oxide semiconductor film, forming a hydrogen capture film over and in contact with the hydrogen permeable film, and releasing hydrogen from the oxide semiconductor film by performing heat treatment. Further, in a method for manufacturing a semiconductor device, the method for forming an oxide semiconductor film is used.

Abstract: According to one embodiment, a non-volatile memory device includes a base layer, a first stacked unit and a second stacked unit disposed above the base layer and arranged in parallel to each other and spaced apart from each other in a first direction, in a plane parallel to the base layer, a first semiconductor layer penetrating the first stacked unit, a second semiconductor layer penetrating in the second stacked unit, the first memory film disposed between the first semiconductor layer and the first stacked unit, and a connecting portion disposed between the base layer and the first stacked unit and between the base layer and the second stacked unit and electrically connecting the first semiconductor layer and the second semiconductor layer. An end portion of the first semiconductor layer is positioned between the connecting portion and the base layer.