Abstract: An organic light-emitting display device includes first through third pixels, wherein each of the first through third pixels comprises a first electrode, a second electrode which faces the first electrode, an organic light-emitting layer which is disposed between the first electrode and the second electrode. The first pixel includes a first color filter material, the second pixel includes a second color filter material, and the third pixel includes a third color filter material. The third pixel comprises a first transmitting region in which the third color filter material is not disposed and which is configured to allow a substantial amount of light emitted from the organic light-emitting layer of the third pixel to transmit therethrough.

Abstract: The present invention generally relates to nanoscale wires and tissue engineering. Systems and methods are provided in various embodiments for preparing cell scaffolds that can be used for growing cells or tissues, where the cell scaffolds comprise nanoscale wires. In some cases, the nanoscale wires can be connected to electronic circuits extending externally of the cell scaffold. Such cell scaffolds can be used to grow cells or tissues which can be determined and/or controlled at very high resolutions, due to the presence of the nanoscale wires, and such cell scaffolds will find use in a wide variety of novel applications, including applications in tissue engineering, prosthetics, pacemakers, implants, or the like. This approach thus allows for the creation of fundamentally new types of functionalized cells and tissues, due to the high degree of electronic control offered by the nanoscale wires and electronic circuits.

Abstract: The invention relates to a method for producing a plurality of optoelectronic semiconductor components (1), comprising the following steps: a) providing a semiconductor layer sequence (2) having a plurality of semiconductor body regions (200); b) providing a plurality of carrier bodies (3), which each have a first contact structure (31) and a second contact structure (32); c) forming a composite (4) having the semiconductor layer sequence and the carrier bodies in such a way that adjacent carrier bodies are separated from one another by interspaces (35) and each semiconductor body area is electrically conductive connected to the first contact structure and the second contact structure of the associated carrier body; and d) separating the composite into the plurality of semiconductor components, wherein the semiconductor components each have a semiconductor body (20) and a carrier body. The invention further relates to an optoelectronic semiconductor component (1).

Abstract: A thin film transistor substrate (2) includes: an auxiliary capacitor electrode (7); a gate insulating film (8) formed on an insulating substrate (4) to cover the auxiliary capacitor electrode (7); a drain electrode (11) formed on the gate insulating film (8) and an oxide semiconductor layer (9); a planarization film (13) formed on a passivation film (12); a capacitor electrode (14) formed on the planarization film (13); an interlayer insulating film (16) formed on the planarization film (13); and a pixel electrode (17) formed on the interlayer insulating film (16) and electrically connected to the drain electrode (11) via a contact hole (18).

Abstract: The present technology relates to a solid-state image sensor, an imaging device, and electronic equipment configured such that an FD is shared by a plurality of pixels to further miniaturize the pixels at low cost without lowering of sensitivity and a conversion efficiency. In a configuration in which a plurality of pixels are arranged with respect to at least either of one of the OCCFs or one of the OCLs, a floating diffusion (FD) is shared by a sharing unit including a plurality of pixels, the plurality of pixels including pixels of at least either of different OCCFs or different OCLs. The present technology is applicable to a CMOS image sensor.

Abstract: A light emitting device includes a package and at least one light emitting element. The package includes a recess portion which has a bottom surface, an opening on a front side opposite to the bottom surface in a front direction vertical to the bottom surface, and an inner peripheral wall connecting the bottom surface and the front side. The bottom surface has distances between opposite sides of the bottom surface and has a longest distance among the distances. The at least one light emitting element is disposed on the bottom surface of the recess portion and has a polygonal shape which has five or more sides and which has a longest diagonal line viewed along the front direction. Each internal angle of the polygonal shape is less than 180°. The longest diagonal line of the polygonal shape is parallel to a lateral line along the longest distance.

Abstract: A semiconductor wafer (100) having a regular pattern of predetermined separation lanes (102) is provided, wherein the predetermined separation lanes (102) are configured in such a way that the semiconductor wafer is singularizable along the regular pattern.

Abstract: A first silicon controlled rectifier has a breakdown voltage in a first direction and a breakdown voltage in a second direction. A second silicon controlled rectifier has a breakdown voltage with a higher magnitude than the first silicon controlled rectifier in the first direction, and a breakdown voltage with a lower magnitude than the first silicon controlled rectifier in the second direction. A bidirectional electrostatic discharge (ESD) structure utilizes both the first silicon controlled rectifier and the second silicon controlled rectifier to provide bidirectional protection.

Abstract: An enhancement-mode GaN transistor with reduced gate leakage current between a gate contact and a 2DEG region and a method for manufacturing the same. The enhancement-mode GaN transistor including a GaN layer, a barrier layer disposed on the GaN layer with a 2DEG region formed at an interface between the GaN layer and the barrier layer, and source contact and drain contacts disposed on the barrier layer. The GaN transistor further includes a p-type gate material formed above the barrier layer and between the source and drain contacts and a gate metal disposed on the p-type gate material, with wherein the p-type gate material including comprises a pair of self- aligned ledges that extend toward the source contact and drain contact, respectively.

Abstract: An LED device and method of manufacture including separately coupling a thin flexible interposer and an LED die to a heat sink structure and then electrically coupling the interposer and the LED die together with a wirebond. A specifically shaped perimeter of an aperture within the interposer negates the need for a cavity or alignment markings within the heat sink structure by limiting the orientation in which the die fits within the aperture. Alternatively, an LED device and method of manufacture include coupling a rigid circuit board to an LED die such that electrical contacts of the die are electrically coupled with electrical input/output terminals of the circuit board. This die/board unit is then able to be coupled to a heat sink structure to form a portion of the device.

Abstract: A see-through organic light emitting display device including a light emitting region having a transparent anode, an organic light emitting layer, and a transparent cathode, and a see-through region having a transparent auxiliary electrode, which is configured to transmit external light. The transparent auxiliary electrode can be made from the same material as the transparent anode and separated from the transparent anode, and the transparent cathode extends into the see-through region so as to be electrically connected with the transparent auxiliary electrode.

Abstract: A wavelength converting member includes silica glass and a plurality of fluorescent material particles including an oxynitride or nitride fluorescent material and dispersed in the silica glass. The plurality of fluorescent material particles include at least two kinds of fluorescent material particles including (i) first fluorescent material particles that emit a fluorescence having a first peak wavelength and (ii) second fluorescent material particles that emit a fluorescence having a second peak wavelength. The wavelength converting member has a density within a range from 0.8 g/cm3 to 1.2 g/cm3.

Abstract: The disclosure relates to a semiconductor device. An exemplary structure for a nanowire structure comprises a first semiconductor material having a first lattice constant and a first linear thermal expansion constant; and a second semiconductor material having a second lattice constant and a second linear thermal expansion constant surrounding the first semiconductor material, wherein a ratio of the first lattice constant to the second lattice constant is from 0.98 to 1.02, wherein a ratio of the first linear thermal expansion constant to the second linear thermal expansion constant is greater than 1.2 or less than 0.8.

Abstract: Techniques for dielectric isolation in bulk nanosheet devices are provided. In one aspect, a method of forming a nanosheet device structure with dielectric isolation includes the steps of: optionally implanting at least one dopant into a top portion of a bulk semiconductor wafer, wherein the at least one dopant is configured to increase an oxidation rate of the top portion of the bulk semiconductor wafer; forming a plurality of nanosheets as a stack on the bulk semiconductor wafer; patterning the nanosheets to form one or more nanowire stacks and one or more trenches between the nanowire stacks; forming spacers covering sidewalls of the nanowire stacks; and oxidizing the top portion of the bulk semiconductor wafer through the trenches, wherein the oxidizing step forms a dielectric isolation region in the top portion of the bulk semiconductor wafer. A nanowire FET and method for formation thereof are also provided.

Abstract: A three-dimensional nonvolatile memory device and a method for fabricating the same include a semiconductor substrate, a plurality of active pillars, a plurality of gate electrodes, and a plurality of supporters. The semiconductor substrate includes a memory cell region and a contact region. The active pillars extend in the memory cell region perpendicularly to the semiconductor substrate. The gate electrodes intersect the active pillars, extend from the memory cell region to the contact region and are stacked on the semiconductor substrate. The supporters extend in the contact region perpendicularly to the semiconductor substrate to penetrate at least one or more of the gate electrodes.

Abstract: A light emitting device includes a base that has an element mounting surface, a light emitting element that is mounted on the element mounting surface and that has maximum light intensity in a directly upward direction, and a coating member that contains a fluorescent body that is excited by light from the light emitting element, and that is constituted by a single layer that coats an upper part of the light emitting element. The fluorescent body exists at a position other than directly above the light emitting element.

Abstract: Semiconductor device packages, packaging methods, and packaged semiconductor devices are disclosed. In some embodiments, a package for a semiconductor device includes a back side interconnect structure, and a winding of an inductor disposed in a material layer of the back side interconnect structure. A molding material is coupled to the back side interconnect structure. The package includes an integrated circuit die mounting region disposed within the molding material.

Abstract: A side-view type light emitting device having a bottom surface thereof as a light emission surface and one side surface thereof as amounting surface for mounting on amounting substrate includes a stacked semiconductor layer having a first semiconductor layer, an active layer, and a second semiconductor layer which are stacked in that order from a side of the bottom surface; a first connecting electrode exposed from the one side surface and electrically connected to the first semiconductor layer; a metal wire having one end thereof electrically connected to an upper surface of the second semiconductor layer; a second connecting electrode exposed from the one side surface and electrically connected to the other end of the metal wire; and a resin layer which covers at least a part of each of the first semiconductor layer, the second semiconductor layer, the first connecting electrode, the second connecting electrode and the metal wire and which is configured to form an upper surface and side surfaces of the ligh

Abstract: The present invention discloses a pixel structure and a manufacturing method thereof, a light-emitting device, an array substrate and a display device. The pixel structure comprises a plurality of pixel units sequentially arranged, each pixel unit comprising a plurality of color sub-pixel units, wherein the color sub-pixel unit of a certain color to which human eyes have poor discriminating power is positioned in a central position of the pixel unit, and the color sub-pixel units of the remaining colors are positioned around the color sub-pixel unit of the certain color, and an area of the color sub-pixel unit of the certain color is larger than that of any one of the color sub-pixel units of the remaining colors.

Abstract: A non-volatile memory device includes a plurality of memory cells. Each memory cell includes a vertical channel, a control gate, a floating gate, and an erase gate disposed on a substrate. The vertical channel extends upwards in a vertical direction. The control gate, the floating gate, and the erase gate surround the vertical channel respectively, and a part of the floating gate is surrounded by the control gate. The erase gate is disposed between the substrate and the floating gate in the vertical direction, and the floating gate include a tip extending toward the erase gate. The vertical channel and electrodes surrounding the vertical channel, such as the control gate, the floating gate, and the erase gate, are used to reduce the area of the memory cell on the substrate of the non-volatile memory device in the present invention. The density of the memory cells may be enhanced accordingly.