Patents Examined by Janice A. Howell
  • Patent number: 5172256
    Abstract: The present invention is a novel and improved variable color/variable density optical system (10) adapted for use in a variety of lens and window applications. The preferred device embodying the invention is a novel optical sunlight protective device (12) incorporating a liquid crystal color lens, a photodetecting sensor component and circuit (18) and oscillating/driving electronic circuit (70), all of the present invention and incorporated in an appropriate frame (24). The lens element (b 14) includes plastic housing (40,42) of a curved shape complementary to any desired fashion design and, a liquid crystalline medium (58) of the novel phase change guest-host type. Combination of the lens construction, homeotropic surface alignment (48, 50) and aforementioned liquid crystal/dye complex brings about the clear, optical distortion-free variable color transmission with broad ranges of color density with incorporated protection against ultraviolet radiation.
    Type: Grant
    Filed: January 5, 1989
    Date of Patent: December 15, 1992
    Inventors: Nicholas L. Sethofer, Eric R. Henderson, deceased
  • Patent number: 5171998
    Abstract: A gamma ray imaging detector is disclosed for use in nuclear medicine applications. The imaging detector includes a single scintillation detector crystal which converts absorbed gamma rays into a plurality of scintillation photons. The scintillation detector crystal emits scintillation light with a spectral distribution for which most of the yield corresponds to wavelengths longer than 475 nanometers and is preferably a thallium doped cesium iodide crystal. An array of photodiodes are arranged along one side of the crystal to receive the scintillation photons which generate an electrical output signal proportional to the number of scintillation photons received by the photodiode. Diodes with low capacitance and electrical noise, such as silicon drift photodiodes, are employed so that the signal generated by the photodiode as a result of the received scintillation photons is readily detectable above the electrical noise from the photodiodes.
    Type: Grant
    Filed: June 14, 1990
    Date of Patent: December 15, 1992
    Inventors: John C. Engdahl, Glenn F. Knoll
  • Patent number: 5172019
    Abstract: In an analog-to-digital converter, a circuit for sampling an analog input signal that has a signal range above and below a ground reference voltage includes a divider circuit scaling the analog input signal down to a lower magnitude such that all values of the scaled analog input signal are above the ground reference voltage. The scaled down analog input signal is applied to a source electrode of a sampling MOSFET. A body-to-source voltage of the sampling MOSFET is maintained at approximately zero volts by applying the scaled down signal to a non-inverting input of a first operational amplifier and applying an output voltage produced by the first operational amplifier to its inverting input and a body electrode of the sampling MOSFET. A gate-to-source voltage of the sampling MOSFET is maintained at approximately 1.
    Type: Grant
    Filed: January 17, 1992
    Date of Patent: December 15, 1992
    Assignee: Burr-Brown Corporation
    Inventors: Jimmy R. Naylor, Mark A. Shill
  • Patent number: 5172011
    Abstract: Latch circuit and method which permit two-phase latches and flip-flops to be intermixed in a system having level sensitive scanning without critical clock requirements. The circuit includes a master latch having a normal data input and a scan data input, and a slave latch connected to the master latch. A differential pair of clock signals is applied to the latches in a complementary manner during a normal mode of operation to load data from the normal data input to the master latch and to transfer the normal data from the master latch to the slave latch, and two separate low frequency non-overlapping scan clock phases are applied to the latches during a level sensitive scanning mode to load data from the scan data input to the master latch and to transfer the scan data from the master latch to the slave latch.
    Type: Grant
    Filed: June 30, 1989
    Date of Patent: December 15, 1992
    Assignee: Digital Equipment Corporation
    Inventors: Dale H. Leuthold, Paul M. Guglielmi
  • Patent number: 5172403
    Abstract: An X-ray exposure apparatus for transferring a pattern of a mask to a wafer includes an X-ray source accommodating chamber; a mask chuck for supporting the mask; a wafer chuck for supporting the wafer; a stage for moving the wafer chuck; a stage accommodating chamber for accommodating therein the mask chuck, the wafer chuck and the stage; a barrel for coupling the X-ray source accommodating chamber with the stage accommodating chamber, to define an X-ray projection passageway; a blocking window provided in the X-ray projection passageway, for isolating the ambience in the X-ray accommodating chamber and the ambience in the stage accommodating chamber from each other; and a gas supply port contributable to fill the stage accommodating chamber with a gas ambience of low X-ray absorption, the gas supply port opening to the X-ray projection passageway, at a position between the blocking window and the mask supported by the mask chuck.
    Type: Grant
    Filed: October 22, 1990
    Date of Patent: December 15, 1992
    Assignee: Canon Kabushiki Kaisha
    Inventors: Yutaka Tanaka, Nobutoshi Mizusawa, Takao Kariya, Shunichi Uzawa, Mitsuaki Amemiya
  • Patent number: 5170074
    Abstract: A flip-flop of a master-slave type of a CMOS structure having no P channel transistor between nodes of the master flip-flop and of the slave flip-flop is provided. Only one P channel MOS transistor is existent in a route of the current controlling a rise time and a trail time of output signals, so that it is possible to function at a high speed.
    Type: Grant
    Filed: March 12, 1991
    Date of Patent: December 8, 1992
    Assignee: NEC Corporation
    Inventor: Yasushi Aoki
  • Patent number: 5170078
    Abstract: A highly stable high-voltage output buffer is provided which may be manufactured using standard CMOS technology. As part of the invention, the effects of voltage drift at one or more of the nodes formed between series connected P or N-channel MOSFET devices are generally reduced or eliminated. The present invention includes compensation circuitry which reduces the effects of parasitic coupling within the MOSFET devices, and which serves to compensate for any voltage drift which may occur at the nodes between series connected devices. In addition, the present invention provides a method and apparatus for increasing the current sourcing capability of a CMOS high-voltage output buffer, even under low supply V.sub.vf conditions, without necessarily increasing the size of the output device. Furthermore, the present invention provides a method and apparatus for reducing the effects of coupling along a shared bias line between a plurality of high-voltage output buffers in accordance with the present invention.
    Type: Grant
    Filed: October 22, 1990
    Date of Patent: December 8, 1992
    Assignee: Gould Inc.
    Inventors: Kelvin K. Hsueh, Brian R. Kauffmann, Gerardus F. Riebeek
  • Patent number: 5170063
    Abstract: An inspection device for detecting defects in a periodic pattern on a semiconductor wafer includes a laser oscillator. In the exposure process, light emitted from the laser oscillator is divided into a subject beam and a reference beam. The subject beam is guided to a semiconductor wafer having a periodic pattern thereon by mirrors and a beam expander. The light scattered from the specimen is collected by a lens on a photographic plate. The reference beam is guided to the photographic plate via a second beam expander and another mirror. The intensity of the reference beam is adjusted to a level at which the reference beams interferes on the photographic plate with the light scattered from defects in the periodic pattern and collected by the lens. Thus, a hologram of the defects in the pattern is recorded on the photographic plate. After development, the photographic plate is returned to its original position and used to form a holographic image of the defects with a transmitted regeneration light beam.
    Type: Grant
    Filed: February 27, 1991
    Date of Patent: December 8, 1992
    Assignee: Mitsubishi Denki Kabushiki Kaisha
    Inventors: Yoko Miyazaki, Hitoshi Tanaka, Nobuyuki Kosaka, Toshimasa Tomoda
  • Patent number: 5170271
    Abstract: A shaped voltage pulse is applied to a polymer dispersed liquid crystal (PDLC) cell to control its transmission characteristics. The voltage has an initially high level that substantially exceeds the PDLC's threshold voltage. The initial voltage duration is relatively short, and is followed by a gradual reduction of the voltage to a level less than the threshold voltage within a given time frame; the voltage is preferably reduced at a generally exponential rate. Fast response is obtained by setting the initial voltage substantially above the voltage level that corresponds to the desired transmission level in the steady state; the voltage decays from its initial level so that the PDLC transmission actually peaks at the desired range. The shaped waveform forces the PDLC to operate on a hysteresis curve along which the reduction in transmission is delayed as the voltage decays, thereby increasing the cell's optical throughput. The invention is particularly applicable to liquid crystal light valves.
    Type: Grant
    Filed: January 31, 1991
    Date of Patent: December 8, 1992
    Assignee: Hughes Aircraft Company
    Inventors: Anna M. Lackner, J. David Margerum, Elena Sherman
  • Patent number: 5170425
    Abstract: An x-ray diagnostics installation has a primary radiation diaphragm disposed in the beam path of an x-ray tube, with the x-rays attenuated by an examination subject being processed through an image intensifier video chain, which includes an image memory. The primary radiation diaphragm is provided with sensors which generate an electrical signal corresponding to the position of the individual diaphragm components of the primary radiation diaphragm, these signals being supplied to a processing stage in the image intensifier video chain. The processing stage acts on the data stored in the image memory so that the effect of the diaphragm can be simulated, and included in the displayed image. The processing stage includes a control computer connected to the sensors, and a simulation circuit for simulating the effect of the primary radiation diaphragm.
    Type: Grant
    Filed: February 5, 1992
    Date of Patent: December 8, 1992
    Assignee: Siemens Aktiengesellschaft
    Inventor: Joerg Haendle
  • Patent number: 5170278
    Abstract: Reflecting faces constituting one or more reflecting face pairs are respectively inclined at 45 degrees with respect to the rotational axis of an optical deflecting element. The reflecting faces are opposed to each other such that these reflecting faces are perpendicular to each other. The reflecting face pairs are arranged with axial symmetry with respect to the rotational axis. A light beam is incident to one of the reflecting faces in parallel to the rotational axis. This light beam is sequentially reflected on this one reflecting face and the other reflecting face constituting the reflecting face pairs together with this one reflecting face. Then, the light beam is returned from the other reflecting face in parallel to the rotational axis and is emitted as a deflected light beam. An optical scanner using the return optical deflecting element and an optical deflecting element is also shown.
    Type: Grant
    Filed: August 2, 1991
    Date of Patent: December 8, 1992
    Assignee: Ricoh Company, Ltd.
    Inventors: Yoshishige Wada, Nobuo Sakuma
  • Patent number: 5168182
    Abstract: A transformer isolates a control circuit from a FET, the control circuit including a clock generator for providing, when enabled, a clock signal to the transformer primary. A PWM input selectively disables the clock generator from providing the clock signal to the transformer primary. The transformer secondary is connected in a full wave centertap configuration for providing a full wave rectified version of the clock signal, the full wave rectified version being a relatively constant DC voltage signal supplied at one level to the FET to turn on the FET when the clock generator is enabled to provide the clock signal to the primary. The centertap configuration provides a relatively constant DC voltage signal at a second level to the FET to turn off the FET when the clock generator is disabled by the PWM input from providing the clock signal to the primary.
    Type: Grant
    Filed: June 24, 1991
    Date of Patent: December 1, 1992
    Assignee: United Technologies Corporation
    Inventors: David C. Salerno, Walter O. Roberts
  • Patent number: 5168181
    Abstract: A spike filtering circuit for a logic signal comprises a signal transfer circuit formed by a first transfer gate followed by a pair of inverters, functionally connected in series between the input terminal and the output terminal of the circuit and a second transfer gate connected between the output terminal and the input node of the first of said two inverters. The two transfer gates are driven in phase opposition to each other by means of a pair of control signals in phase opposition to each other which are generated by a control circuit functioning in a feedback mode. Basically the control circuit is formed by an exclusive-OR gate having two inputs connected to the output terminal of the circuit directly and through a delay network, respectively. Through an output node of the exclusive-OR gate is produced a first control signal from which the pair of control signals in phase opposition to each other are derived by means of inverting stages.
    Type: Grant
    Filed: May 23, 1991
    Date of Patent: December 1, 1992
    Assignee: SGS-Thomson Microelectronics s.r.l.
    Inventors: Antonella Baiocchi, Angelo Alzati, Aldo Novelli
  • Patent number: 5168384
    Abstract: A miniature liquid crystal display panel device comprises a plurality of column and row terminals. On a squarish frame holder is formed an opening for a light passage in the middle of an enclosing wall and a support portion for mounting the display panel. First and second IC units each including a flexible wiring film and an IC chip are disposed outside the enclosing wall of the holder. A flexible circuit connector for respectively connecting first and second IC units to a control circuit is wound around the outside of the holder. A light source for projecting the display panel is disposed opposite to the display panel in the rear side of the device.
    Type: Grant
    Filed: February 14, 1991
    Date of Patent: December 1, 1992
    Assignee: Casio Computer Co., Ltd.
    Inventor: Yasuo Genba
  • Patent number: 5168174
    Abstract: A charge-pump circuit implements ramp control, steady-state regulation and trimming of the negative voltage pulses. The circuit includes a negative-voltage charge-pump subcircuit having multiple phase inputs, a phase-enable input, an output, a supply voltage, a reference voltage, a ramp-control subcircuit for controlling the rate of change of the voltage at the output of charge-pump subcircuit, and an amplitude-control subcircuit for controlling the amplitude of the voltage at the output of the charge-pump subcircuit. The ramp-control has an input coupled to the output of the charge-pump subcircuit and an output coupled to the phase-enable input of the charge-pump subcircuit. The amplitude-control subcircuit has an input to the output of the charge-pump subcircuit and has an output coupled to the phase-enable input of the charge-pump subcircuit.
    Type: Grant
    Filed: July 12, 1991
    Date of Patent: December 1, 1992
    Assignee: Texas Instruments Incorporated
    Inventors: Giovanni Naso, Giovanni Santin, Sebastiano D'Arrigo
  • Patent number: 5168382
    Abstract: An optically addressed liquid crystal light valve includes a first substrate on which a plurality of liquid crystal driving circuits are formed, a second substrate provided with a transparent electrode, and a ferroelectric liquid crystal sandwiched between the two substrates. Each liquid crystal driving circuit includes a plurality of photodetectors and a logic circuit. An optical logic device includes an optically addressed liquid crystal light valve explained above and a plurality of masks for selectively transmit a plurality of lights. The masks may be replaced by a wavelength selecting filter including a plurality of regions each transmit a light having a specific wavelength to a corresponding photodetector of the light valve.
    Type: Grant
    Filed: November 15, 1991
    Date of Patent: December 1, 1992
    Assignee: NEC Corporation
    Inventor: Susumu Tsujikawa
  • Patent number: 5168179
    Abstract: A balanced modulator for use with auto-zero networks is described. The present invention is a switched capacitor balanced modulator suitable for use in auto-zero networks where a valid input signal is available only at one phase. The present invention changes the polarity of the input signal by adjusting a switched feedback capacitor, making it possible for the switched input capacitor to sample only at one (valid) phase. The balanced modulator of the present invention may be utilized with first order auto-zero low pass filters or other switched capacitor blocks, such as gain blocks, first order high pass filters, etc.
    Type: Grant
    Filed: October 1, 1991
    Date of Patent: December 1, 1992
    Assignee: Silicon Systems, Inc.
    Inventor: Mehrdad Negahban-Hagh
  • Patent number: 5166632
    Abstract: A limiter circuit utilizes an RC circuit to provide negative feedback of the average value of the output signal of an amplifier, which may be an op-amp or a comparator, to the inverting input of the amplifier. The midpoint of the amplifier supply voltage is applied to the non-inverting input so that the amplifier operates in the linear range. This, combined with the elimination of the effects of offset produced by the negative feedback, results in a limiter circuit with increased sensitivity to small input signals and therefore extended dynamic range. Where a following circuit would be adversely affected by noise, hysteresis provided by positive feedback applied to the non-inverting input of the amplifier causes the limiter circuit to oscillate, at a frequency determined by the magnitude of the positive feedback and the time constant of the RC circuit providing the negative feedback, for input signals having an amplitude below a threshold set by the magnitude of the positive feedback.
    Type: Grant
    Filed: October 10, 1991
    Date of Patent: November 24, 1992
    Assignee: Westinghouse Electric Corp.
    Inventor: Raymond W. MacKenzie
  • Patent number: 5166543
    Abstract: A current regulating circuit for an inductive load (12) is proposed, in particular for an electrohydraulic pressure regulator for an automatic transmission of a motor vehicle. A push-pull end stage (16) controls the flow of current through the load (12). Connected in series with the load (12) is a measuring resistor (11), the voltage drop of which, as an actual current value, is applied along with a command current value to a comparison stage (23, 34), by the clocked output signal of which the end stage (16) can be controlled. The measuring resistor (11) is disposed between the load (12) and a first switch transistor (10) of the end stage (16). The potential at one of the pickups (19, 20) of the measuring resistor (11) is provided as a variable reference potential for an auxiliary voltage source (31) supplying the comparison stage (23, 34), which source has switch means (40) for generating an auxiliary voltage (Uh) that is constant relative to the variable reference potential.
    Type: Grant
    Filed: September 12, 1991
    Date of Patent: November 24, 1992
    Assignee: Robert Bosch GmbH
    Inventors: Claus Schneider, Karsten-Erik Thiele
  • Patent number: 5166553
    Abstract: A semiconductor circuit including first and second FET's for delivering an output signal without being affected by a change in threshold voltage of the FET's is disclosed. According to one practical form of the semiconductor circuit, the drain-source current path of an additional FET whose gate and source are shorted to each other, is connected in parallel to the drain-source current path of the first FET whose gate and drain are shorted to each other, to make the voltage-current characteristic of the second FET agree with that of the parallel combination of the first and additional FET's. According to another practical form of the semiconductor circuit, a voltage dividing circuit is connected in parallel to the drain-source current path of the first FET, and a divided output voltage from the voltage dividing circuit is applied between the gate and source of each of the first and second FET's.
    Type: Grant
    Filed: June 12, 1989
    Date of Patent: November 24, 1992
    Assignee: Hitachi, Ltd.
    Inventors: Nobuo Kotera, Kiichi Yamashita, Hirotoshi Tanaka, Satoshi Tanaka, Yasushi Hatta, Minoru Nagata