Abstract: Provided are a semiconductor device, a method of manufacturing the semiconductor device, and an electronic system adopting the same. The semiconductor device includes a semiconductor pattern, which is disposed on a semiconductor substrate and has an opening. The semiconductor pattern includes a first impurity region having a first conductivity type and a second impurity region having a second conductivity type different from the first conductivity type. A peripheral transistor is disposed between the semiconductor substrate and the semiconductor pattern. A first peripheral interconnection structure is disposed between the semiconductor substrate and the semiconductor pattern. The first peripheral interconnection structure is electrically connected to the peripheral transistor. Cell gate conductive patterns are disposed on the semiconductor pattern. Cell vertical structures are disposed to pass through the cell gate conductive patterns and to be connected to the semiconductor pattern.

Abstract: There is proposed a light source comprising: a semiconductor diode structure adapted to generate light; and an optical enhancement section above the semiconductor diode structure and adapted to output light from the semiconductor diode structure. A partially-reflective layer covers at least a portion of the top of the optical enhancement section and is adapted to reflect a portion of the output light towards the optical enhancement section. The partially-reflective layer has a light transmittance characteristic that varies laterally.

Abstract: Methods of aligning a number of physical layers to a pattern formed via multi-patterning are disclosed. A method may include determining a misalignment vector between a first layer and a second layer used to form a pattern via multi-patterning. The method may also include calculating, based on the misalignment vector between the first layer and the second layer, a center position of the pattern. Further, the method may include aligning a third layer to center position of the pattern. A computing system and a processing system are also described.

Abstract: According to one embodiment, a semiconductor device includes a base, a memory cell region on the base comprising a first plurality of conductive layers and a second plurality of insulating layers, wherein an insulating layer extends between, and separates, each two adjacent conductive layers of the first plurality of conductive layers. A first stacked body and a second stacked body are located on the base, and includes a plurality of insulating layers and a plurality of conductive layers fewer than the number of first conductive layers, and an insulating layer extends between, and separates, each two adjacent conductive layers of the plurality of conductive layers in each stacked body. The end portions of the stacked bodies include a stair portion having a stair-like shape wherein a surface of each of the conductive layers thereof is exposed.

Abstract: In order to suppress a film from being formed in a gap between a mask and a substrate, a technology of improving adhesion between the mask and the substrate is provided. A film-forming method includes the step of suspending a mask MK by a suspension portion HU in a state in which the suspension portion HU is supported by a supporting portion SU and the step of bringing the mask MK suspended by the suspension portion HU into contact with a glass substrate GS in the state in which the suspension portion HU is supported by the supporting portion SU.

Abstract: A display apparatus comprises a pixel including a plurality of sub pixels. Each of the sub pixels includes a current driven light emitting device, a transistor for supplying an electric current to the light emitting device and a capacitive element for maintaining a gate voltage of the transistor. The capacitive element of one sub pixel and the capacitive element of the other sub pixel at least partially overlap each other.

Abstract: A method of producing a quantum circuit includes forming a mask on a substrate to cover a first portion of the substrate, implanting a second portion of the substrate with ions, and removing the mask, thereby providing a nanowire. The method further includes forming a first lead and a second lead, the first lead and the second lead each partially overlapping the nanowire. In operation, a portion of the nanowire between the first and second leads forms a quantum dot, thereby providing a quantum dot Josephson junction. The method further includes forming a third lead and a fourth lead, one of the third and fourth leads partially overlapping the nanowire, wherein the third lead is separated from the fourth lead by a dielectric layer, thereby providing a Dolan bridge Josephson junction. The nanowire is configured to connect the quantum dot Josephson junction and the Dolan bridge Josephson junction in series.

Abstract: A semiconductor device includes: first, second, and third tiers formed on a substrate, wherein the first tier is formed over the substrate, the second tier is formed over the first tier, and the third tier is formed over the second tier, wherein the second tier comprises a first interconnection line that is configured to transmit a signal, and wherein a portion of the first tier disposed directly under the first interconnection line of the second tier lacks any interconnection lines and a portion of the third tier disposed directly above the first interconnection line of the second tier lacks any interconnection lines.

Abstract: An electronic device and manufacturing method of the electronic device are disclosed. The manufacturing method includes: providing a substrate; forming a thin film circuit on the substrate, wherein the thin film circuit comprises at least one thin film transistor and at least one conductive trace; forming at least one first connection pad on the substrate, wherein the first connection pad is electrically connected with the thin film transistor through the conductive trace; disposing the substrate on a driving circuit board, wherein the driving circuit board comprises at least one second connection pad adjacent to and corresponding to the first connection pad; and forming a conductive member covering at least a part of the second connection pad and the first connection pad, wherein the second connection pad is electrically connected with the first connection pad through the conductive member.

Abstract: A semiconductor device and method for forming the semiconductor device is provided. The semiconductor device includes an integrated circuit having through vias adjacent to the integrated circuit die, wherein a molding compound is interposed between the integrated circuit die and the through vias. The through vias have a projection extending through a patterned layer, and the through vias may be offset from a surface of the patterned layer. The recess may be formed by selectively removing a seed layer used to form the through vias.

Abstract: An OLED substrate and a manufacturing method thereof, the OLED substrate includes a substrate, and an OLED device in a sub-pixel region on the substrate. The OLED device includes an organic layer having a non-uniform thickness. The OLED substrate further includes a transmittance adjusting layer in the sub-pixel region. The transmittance of a portion of the transmittance adjusting layer corresponding to a thicker portion of the organic layer is higher than the transmittance of a portion of the transmittance adjusting layer corresponding to a thinner portion of the organic layer. The transmittance adjusting layer is located on a light exit side of the organic layer such that light emitted from the organic layer passes through the transmittance adjusting layer when the OLED substrate is in operation.

Abstract: A U-shaped gate dielectric structure is provided that has a horizontal gate dielectric portion having a vertical thickness, and a vertical gate dielectric wall portion extending upwards from the horizontal gate dielectric portion. The vertical gate dielectric wall portion has a lateral thickness that is greater than the vertical thickness of the horizontal gate dielectric portion. The U-shaped gate dielectric structure houses a gate conductor portion. Collectively, the U-shaped gate dielectric structure and the gate conductor portion provide a functional gate structure that has reduced capacitance.

Abstract: Processes for providing nitridation on a workpiece, such as a semiconductor, are provided. In one example implementation, a method can include supporting a workpiece on a workpiece support. The method can include exposing the workpiece to species generated from a capacitively coupled plasma to provide nitridation on the workpiece. The method can also include exposing the workpiece to species generated form an inductively coupled plasma to provide nitridation on the workpiece.

Abstract: Embodiments of methods and apparatus for filling a feature disposed in a substrate are disclosed herein. In some embodiments, a method for filling a feature disposed in a substrate includes (a) depositing a metal within the feature to a first predetermined thickness in a first process chamber; (b) depositing the metal within the feature to a second predetermined thickness in a second process chamber; (c) etching the metal deposited in (b) to remove an overhang of the metal at a top of the feature in a third process chamber different than the first and second process chambers; and (d) subsequent to (c), filling the feature with the metal in a fourth process chamber different than the first and third process chambers.

Abstract: Techniques and apparatus are provided for improved diagnostics of downhole dynamometer data for control and troubleshooting of reciprocating rod lift systems. A method for pump fillage determination for a reciprocating rod lift system is provided. The method generally includes measuring downhole data during a pump cycle, wherein the downhole data comprises a first plurality of data points associated with an upstroke of the pump cycle and a second plurality of data points associated with a downstroke of the pump cycle, each data point comprising a rod position value and an associated rod load value; converting the data points to non-dimensional data points, calculating non-dimensional slope values between non-dimensional data points; and determining pump fillage based, at least part, on the calculated non-dimensional slope values.

Abstract: Semiconductor devices and methods for manufacturing the same are disclosed. In an embodiment, a method of manufacturing a semiconductor device may include providing a substrate having a recess; epitaxially forming a first layer including a doped semiconductor material within the recess; and epitaxially forming a second layer including an undoped semiconductor material over at least a portion of the recess.

Abstract: Various embodiments of the present application are directed towards a method to integrate NVM devices with a logic or BCD device. In some embodiments, an isolation structure is formed in a semiconductor substrate. The isolation structure demarcates a memory region of the semiconductor substrate, and further demarcates a peripheral region of the semiconductor substrate. The peripheral region may, for example, correspond to BCD device or a logic device. A doped well is formed in the peripheral region. A dielectric seal layer is formed covering the memory and peripheral regions, and further covering the doped well. The dielectric seal layer is removed from the memory region, but not the peripheral region. A memory cell structure is formed on the memory region using a thermal oxidation process. The dielectric seal layer is removed from the peripheral region, and a peripheral device structure including a gate electrode is formed on the peripheral region.

Abstract: Provided are a display substrate and a preparation method thereof, a display panel, and a display device. The display substrate includes a substrate and a plurality of pixel units on the substrate. The pixel unit comprises a plurality of functional layers that are sequentially arranged in a direction away from the substrate. At least one of the plurality of functional layers, which is close to the substrate, constitutes a vertical thin film transistor (VTFT). At least one of the plurality of functional layers, which is away from the substrate, constitutes an organic light-emitting transistor (OLET). An orthographic projection region of the OLET on the substrate and an orthographic projection region of the VTFT on the substrate at least partially overlap.

Abstract: A semiconductor device includes a substrate, a semiconductor element, a ground pad, an insulating coating member, a conductive bonding member, and a conductive cap. The inner peripheral end of a bottom of the conductive cap is disposed at a side close to the inner periphery of the insulating coating member relative to the outer peripheral end of the insulating coating member. The bottom has a shape in which the distance between the main surface and itself decreases continuously from its outer peripheral end toward its inner peripheral end.

Abstract: A method of preparation of focal plane arrays of infrared bolometers includes processing carbon nanotubes to increase a temperature coefficient of resistance (TCR), followed by patterning to form focal plane arrays for infrared imaging.