Abstract: An array substrate is disclosed. The array substrate may include a base substrate, gate lines and data lines intersecting the gate lines on the base substrate. The gate lines and the data lines may define a plurality of pixel regions. Each of at least some of the plurality of the pixel regions may be provided with an image sensor. The image sensor may include a sensitive element, a first electrode at one end of the sensitive element, and a second electrode at the other end of the sensitive element. The image sensor may be configured to sense light having image information.

Abstract: Discussed are a device for self-assembling semiconductor light-emitting diodes, in which the device includes an assembly chamber having a space for accommodating a fluid; a magnetic field forming part having at least one magnet for applying a magnetic force to the semiconductor light-emitting diodes dispersed in the fluid and a moving part for changing positions of the at least one magnet so that the semiconductor light-emitting diodes move in the fluid; and a substrate chuck having a substrate support part configured to support a substrate, and a vertical moving part for lowering the substrate so that one surface of the substrate is in contact with the fluid in a state in which the substrate is supported by the substrate support part, wherein the vertical moving part provided at the substrate chuck lowers the substrate on to the fluid so that a force of buoyancy by the fluid is applied to the substrate.

Abstract: According to one embodiment, a semiconductor memory device includes a stacked body including a plurality of electrode members and a plurality of insulating members, each of the electrode members and each of the insulating members being stacked alternately in a first direction on the substrate. The semiconductor memory device also includes a memory hole that extends in the stacked body in the first direction and a semiconductor member that is disposed to extend in the memory hole in the first direction. The semiconductor memory device also includes a memory member that is disposed between the semiconductor member and the plurality of electrode members. The plurality of electrode members including a first electrode member and a second electrode member, a thickness of the memory member at the position of the first electrode member being greater than a thickness of the memory member at the position of the second electrode member.

Abstract: A method of etching a substrate including an etching film and a mask formed on the etching film is provided. The mask includes a first pattern of a first recess having a first opening and a second pattern of a second recess having a second opening. The method includes etching the etching film to a predetermined depth; depositing a protective film on the mask after the etching; and etching the etching film after the depositing. The first opening is smaller than the second opening. As a result of the depositing, the first opening of the first pattern is clogged and the second opening of the second pattern is not clogged.

Abstract: A semiconductor device and a method of manufacturing a semiconductor device may be provided. The semiconductor device may include first and second vertical conductive patterns isolated from each other by a first slit. The semiconductor device may include at least one first half conductive pattern extending toward a first region disposed at one side of the first slit from the first vertical conductive pattern. The semiconductor device may include at least one second half conductive pattern extending toward a second region disposed at the other side of the first slit from the second vertical conductive pattern.

Abstract: The technology relates to an integrated circuit (IC) package. The IC package may include a substrate. An IC die may be mounted to the substrate. One or more photonic modules may be attached to the substrate and one or more serializer/deserializer (SerDes) interfaces may connect the IC die to the one or more photonic modules. The IC die may be an application specific integrated circuit (ASIC) die and the one or more photonic modules may include a photonic integrated circuit (PIC) and fiber array. The one or more photonic modules may be mounted to one or more additional substrates which may be attached to the substrate via one or more sockets.

Abstract: A fully depleted silicon on insulator (FDSOI) is employed to reduce diffusion leakage (e.g., gate induced drain leakage, junction leakage, etc.) associated with the diffusion regions of a pixel cell. The buried oxide (BOX) layer, for example, fully isolates the transistor channel region, such as an (N) channel region of the pixel cell from the photodiode(s) of the pixel region, eliminating the junction leakage path, thus leading to a reduction in diffusion leakage and an increase device operation speed. An increase of full well capacity can also be realized by the absence of isolation structure, such as trench isolation or isolation implant structure.

Abstract: Provided is a memory device including a substrate, a plurality of stack structures, a spacer, a dielectric layer, and a plurality of contact plugs. The stack structures are disposed on the substrate. The spacer is embedded in the stack structures, so that a width of an upper portion of the stack structures is less than a width of a lower portion thereof. The dielectric layer conformally covers the stack structures and the spacer. The contact plugs are respectively disposed on the substrate between the stack structures.

Abstract: A semiconductor device includes a first transistor, a second transistor and a third transistor provided on a substrate, the first to third transistors respectively including source and drain regions spaced apart from each other, a gate structure extending in a first direction on the substrate and interposed between the source and drain regions, and a channel region connecting the source and drain regions to each other. A channel region of the second transistor and a channel region of the third transistor respectively include a plurality of channel portions, the plurality of channel portions spaced apart from each other in a second direction, perpendicular to an upper surface of the substrate, and connected to the source and drain regions, respectively. A width of a channel portion of the third transistor in the first direction is greater than a width of a channel portion of the second transistor in the first direction.

Abstract: A magnetic property measuring system may include a stage configured to load a sample and to rotate the sample about a rotation axis such that the stage rotates the sample by a rotation angle, the rotation axis extending normal to a top surface of the sample. The magnetic property measuring system may further include a polarizer having a first polarization axis, and an analyzer having a second polarization axis. The polarizer and the analyzer may enable the first and second polarization axes to be independently rotated based on the rotation angle of the sample.

Abstract: A first region is formed by injecting a first condition type first dopant into a surface layer portion of an IGBT section of a semiconductor substrate. A second region is formed by injecting a second condition type second dopant into a region of the IGBT section shallower than the first region. An amorphous third region is formed by injecting the first conduction type third dopant into a surface layer portion of a diode section at a concentration higher than that of the second dopant. Thereafter, the IGBT section and the diode section are laser-annealed under conditions in which the third region is partially melted and the first dopant is activated. Subsequently, a surface layer portion which is shallower than the second injection region in the entire region of the IGBT section and the diode section is melted and crystallized by annealing the IGBT section and the diode section.

Abstract: A semiconductor device has a plurality of semiconductor die. A first prefabricated insulating film is disposed over the semiconductor die. A conductive layer is formed over the first prefabricated insulating film. An interconnect structure is formed over the semiconductor die and first prefabricated insulating film. The first prefabricated insulating film is laminated over the semiconductor die. The first prefabricated insulating film includes glass cloth, glass fiber, or glass fillers. The semiconductor die is embedded within the first prefabricated insulating film with the first prefabricated insulating film covering first and side surfaces of the semiconductor die. The interconnect structure is formed over a second surface of the semiconductor die opposite the first surface. A portion of the first prefabricated insulating film is removed after disposing the first prefabricated insulating film over the semiconductor die.

Abstract: A semiconductor memory device includes a memory chip defined with a first pad on one surface thereof; and a circuit chip defined with a second pad which is coupled with the first pad, on one surface thereof bonded with the one surface of the memory chip. The memory chip comprising: a memory cell array; a bit line disposed in a first wiring layer between the one surface and the memory cell array, and separated into a first bit line section and a second bit line section; and a power pad disposed in a space between the first bit line section and the second bit line section in the first wiring layer, and coupled with the first pad.

Abstract: A semiconductor device has a top metal layer, a first passivation layer over the top metal layer, a first redistribution layer over the first passivation layer, a first polymer layer, and a first conductive via extending through the first polymer layer. The first polymer layer is in physical contact with the first passivation layer.

Abstract: A substrate rotation mechanism rotates the substrate holder about a central axis. A top plate opposes the upper surface of the substrate and rotates about the central axis. A gas supply part supplies a treatment atmospheric gas to a radial central part of a lower space that is a space below the top plate. An ion generator generates and supplies ions to the treatment atmospheric gas supplied from the gas supply part. Then, in a state in which the top plate is positioned lower than when the substrate is transported into the apparatus, the treatment atmospheric gas that contains the ions is supplied to the lower space to form an ion stream that spreads radially outward from the radial central part of the lower space while rotating the substrate holder and the top plate. Accordingly, charges can be dissipated from the top plate with a simple structure.

Abstract: A packaged semiconductor die with a bumpless die-package interface and methods of fabrication are described. For example, a semiconductor package includes a substrate having a land side with a lowermost layer of conductive vias. A semiconductor die is embedded in the substrate and has an uppermost layer of conductive lines, one of which is coupled directly to a conductive via of the lowermost layer of conductive vias of the substrate. In another example, a semiconductor package includes a substrate having a land side with a lowermost layer of conductive vias. A semiconductor die is embedded in the substrate and has an uppermost layer of conductive lines with a layer of conductive vias disposed thereon. At least one of the conductive lines is coupled directly to a conductive via of the semiconductor die which is coupled directly to a conductive via of the lowermost layer of conductive vias of the substrate.

Abstract: In some embodiments, the present disclosure relates to a three dimensional (3D) integrated circuit (IC) stack, including a first IC die having a first substrate and a first interconnect structure over a frontside of the first substrate; a second IC die having a second substrate and a second interconnect structure over the frontside of the second substrate; and a third IC die vertically between the first and second IC dies and having a third substrate, a third interconnect structure over the frontside of the third substrate, and a third bonding structure over a backside of the third substrate. A heat dissipation path extends from the third substrate to at least the first or second substrate, and includes a backside contact that extends from the third bonding structure to the backside of the third substrate and that is thermally coupled to at least the first or second interconnect structure.

Abstract: A method of manufacturing a semiconductor device includes providing, in a housing, an insulating substrate having a metal pattern, a semiconductor chip, a sinter material applied on the semiconductor chip, and a terminal, providing multiple granular sealing resins supported by a grid provided in the housing, heating an inside of the housing until a temperature thereof reaches a first temperature higher than a room temperature and thereby discharging a vaporized solvent of the sinter material out of the housing via a gap of the grid and a gap of the sealing resins, and heating the inside of the housing until the temperature thereof reaches a second temperature higher than the first temperature and thereby causing the melted sealing resins to pass the gap of the grid and form a resin layer covering the semiconductor chip.

Abstract: A display panel may include a first display substrate, a second display substrate disposed over the first display substrate, and a sealing member bonding the first display substrate and the second display substrate. The sealing member may include a frit sealing member including an outer region and an inner region, with the inner region disposed next to an inner side of the outer region and having a first crystallization temperature lower than a second crystallization temperature of the outer region, and an organic sealing member disposed next to an inner side of the frit sealing member.

Abstract: A metal is formed into an opening that is located in an interlayer dielectric (ILD) material that laterally surrounds a semiconductor fin of a partially fabricated vertical transistor and on a physically exposed topmost surface of the semiconductor fin. A patterned material stack of, and from bottom to top, a membrane and a doped amorphous semiconductor material layer is formed on the metal and a topmost surface of the ILD material. A metal induced layer exchange anneal is then employed in which the metal and doped semiconductor material change places such that the doped semiconductor material is in direct contact with the topmost surface of the semiconductor fin. The exchanged doped semiconductor material, which provides a top source/drain structure of the vertical transistor, may have a different crystalline orientation than the topmost surface of the semiconductor fin.