Abstract: A method includes forming a bottom source/drain contact plug in a bottom inter-layer dielectric. The bottom source/drain contact plug is electrically coupled to a source/drain region of a transistor. The method further includes forming an inter-layer dielectric overlying the bottom source/drain contact plug. A source/drain contact opening is formed in the inter-layer dielectric, with the bottom source/drain contact plug exposed through the source/drain contact opening. A dielectric spacer layer is formed to have a first portion extending into the source/drain contact opening and a second portion over the inter-layer dielectric. An anisotropic etching is performed on the dielectric spacer layer, and a remaining vertical portion of the dielectric spacer layer forms a source/drain contact spacer. The remaining portion of the source/drain contact opening is filled to form an upper source/drain contact plug.

Abstract: A substrate processing apparatus includes a liquid processing module, including a carry-out/in port of a substrate, in which a first liquid processing device and a second liquid processing device provided at a position farther from the carry-out/in port than the first liquid processing device is are provided; and a transfer device configured to carry the substrate out from and into the liquid processing module. The first liquid processing device performs a first liquid processing on the substrate. The second liquid processing device performs a second liquid processing on the substrate before or after the first liquid processing. The transfer device includes a substrate holder configured to be moved back and forth in a first horizontal direction, and carries the non-processed substrate into the first liquid processing device through the carry-out/in port and carries the processed substrate out from the first liquid processing device through the carry-out/in port.

Abstract: Provided are a first photoelectric conversion unit, a second photoelectric conversion unit having a smaller electric charge amount to be converted per unit time than the first photoelectric conversion unit, a charge accumulation unit that accumulates an electric charge generated by the second photoelectric conversion unit, a charge voltage conversion unit, a first transfer gate unit that transfers an electric charge from the first photoelectric conversion unit to the charge voltage conversion unit, a second transfer gate unit that couples potentials of the charge voltage conversion unit and the charge accumulation unit, a third transfer gate unit that transfers an electric charge from the second photoelectric conversion unit to the charge accumulation unit, an overflow path formed under a gate electrode of the third transfer gate unit and transfers an electric charge overflowing from the second photoelectric conversion unit to the charge accumulation unit, and a light reducing unit that reduces light to enter

Abstract: In a method of manufacturing a semiconductor device, first and second gate structures are formed. The first (second) gate structure includes a first (second) gate electrode layer and first (second) sidewall spacers disposed on both side faces of the first (second) gate electrode layer. The first and second gate electrode layers are recessed and the first and second sidewall spacers are recessed, thereby forming a first space and a second space over the recessed first and second gate electrode layers and first and second sidewall spacers, respectively. First and second protective layers are formed in the first and second spaces, respectively. First and second etch-stop layers are formed on the first and second protective layers, respectively. A first depth of the first space above the first sidewall spacers is different from a second depth of the first space above the first gate electrode layer.

Abstract: A semiconductor structure is disclosed. The semiconductor structure includes: a substrate of a first conductivity; a first region of the first conductivity formed in the substrate; a second region of the first conductivity formed in the first region, wherein the second region has a higher doping density than the first region; a source region of a second conductivity formed in the second region; a drain region of the second conductivity formed in the substrate; a pickup region of the first conductivity formed in the second region and adjacent to the source region; and a resist protective oxide (RPO) layer formed on a top surface of the second region. An associated fabricating method is also disclosed.

Abstract: A semiconductor manufacturing apparatus according to an embodiment includes: a stage to have a plurality of pins to hold a semiconductor substrate having a first surface on which a film to be etched is formed and a second surface positioned on an opposite side to the first surface; a nozzle to eject a liquid chemical toward the first surface of the semiconductor substrate from above the stage; and an optical measurer to radiate light toward the second surface of the semiconductor substrate from a side of the stage during ejection of the liquid chemical, and to measure a displacement amount of the semiconductor substrate based on a state of reception of light reflected on the second surface.

Abstract: An apparatus for heat-treating a substrate includes: a stage where the substrate is disposed; a heating part configured to change an output; a first temperature measurement part configured to measure a temperature at which the substrate is heated; a second temperature measurement part configured to measure the temperature, and having a level of measurement accuracy which is lower than that of the first temperature measurement part in a first temperature region and is higher than that of the first temperature measurement part in a second temperature region; a temperature calculator configured to calculate a weighted average temperature of the temperatures measured by the first and second temperature measurement parts if a reference temperature is in a temperature range between the first and second temperatures, and configured to change a weight of the weighted average temperature; and a controller configured to control the output based on the weighted average temperature.

Abstract: Stacked thermal process chamber module for remote radiative heating of semiconductor device workpieces. A stacked thermal process module may include a stack of thermal process chambers and one or more generators of electromagnetic radiation. The electromagnetic radiation may be transported from a generator remote from the process chambers through one or more waveguides, thereby minimizing the volume and/or cleanroom footprint of the stacked thermal process chamber module. A waveguide may terminate in a process chamber so that electromagnetic radiation delivered during a thermal process may be coupled into one or more materials of the workpiece. The radiative heating process may overcome many of the limitations of thermal process chambers that instead employ a local heat source located within a process chamber.

Abstract: A light-receiving device includes at least one pixel. The at least one pixel includes a first electrode; a second electrode; and a photoelectric conversion layer between the first electrode and the second electrode. The photoelectric conversion layer is configured to convert incident infrared light into electric charge. The photoelectric conversion layer has a first section and a second section. The first section is closer to the first electrode than the second section, and the second section is closer to the second electrode than the first section. At least one of the first section and the second section have a plurality of surfaces.

Abstract: Disclosed herein is an apparatus and method for annealing semiconductor substrates. In one example the method of annealing substrates in a processing chamber includes loading a plurality of substrates into an internal volume of the processing chamber. The method includes flowing a processing fluid through a gas conduit into the internal volume. The method further includes measuring a temperature of the gas conduit at one or more position utilizing one or more temperature sensors. The processing fluid in the gas conduit and the internal volume are maintained at a temperature above a condensation point of the processing fluid.

Abstract: A lithographic process is used to form a plurality of target structures distributed at a plurality of locations across a substrate and having overlaid periodic structures with a number of different overlay bias values distributed across the target structures. At least some of the target structures comprising a number of overlaid periodic structures (e.g., gratings) that is fewer than said number of different overlay bias values. Asymmetry measurements are obtained for the target structures. The detected asymmetries are used to determine parameters of a lithographic process. Overlay model parameters including translation, magnification and rotation, can be calculated while correcting the effect of bottom grating asymmetry, and using a multi-parameter model of overlay error across the substrate.

Abstract: A flare-blocking image sensor includes large pixels and small pixels, a microlens, and an opaque element. The large pixels and small pixels form a first and second pixel array respectively, each having a pixel pitch Px and Py. The second pixel array is offset from the first pixel array by ½Px and ½Py. A first large pixel of the large pixels is between and collinear with a first and a second small pixel separated by ?{square root over (Px2+Py2 )} in a first direction and each having a width W less than both pixel pitch Px and Py. The microlens is aligned with the first large pixel. The opaque element is between the first large pixel and the microlens and extends, in the first direction, less than ½(?{square root over (Px2+Py2)}?W) from the first small pixel toward the second small pixel. The opaque element has a width perpendicular to the first direction not exceeding width W.

Abstract: Disclosed herein is an apparatus and method for annealing semiconductor substrates. In one example a temperature-controlled fluid circuit includes a condenser configured to fluidly connect to an internal volume of a processing chamber. The processing chamber has a body, the internal volume is within the body. The condenser is configured to condense a processing fluid into liquid phase. A source conduit includes a first terminal end that couples to a first port on the body of the processing chamber. The source conduit includes a second terminal end. The first terminal end couples to a gas panel. The gas panel is configured to provide a processing fluid into the internal volume of the processing chamber. A gas conduit includes a first end. The first end couples to the condenser and a second end. The second end is configured to couple to a second port on the body of the processing chamber.

Abstract: A finFET device and methods of forming a finFET device are provided. The method includes depositing a dummy gate over and along sidewalls of a fin extending upwards from a semiconductor substrate, forming a first gate spacer along a sidewall of the dummy gate, and plasma-doping the first gate spacer with carbon to form a carbon-doped gate spacer. The method further includes forming a source/drain region adjacent a channel region of the fin and diffusing carbon from the carbon-doped gate spacer into a first region of the fin to provide a first carbon-doped region. The first carbon-doped region is disposed between at least a portion of the source/drain region and the channel region of the fin.

Abstract: A structural body includes a first dielectric layer and a second dielectric layer which is in contact with the first dielectric layer and which has a refractive index different from that of the first dielectric layer. The second dielectric layer includes at least two dielectric films different in hydrogen concentration from each other. The interface between the first dielectric layer and the second dielectric layer has periodic first irregularities.

Abstract: An inductor is disclosed. The inductor includes a vertically coiled conductor, a metal contact coupled to a first end of the vertically coiled conductor, and a dielectric material coupled to the metal contact. A tunable high permittivity component is coupled to a second end of the vertically coiled conductor.

Abstract: A stacked die structure for a semiconductor device generally includes a primary level with a first die formed in a wafer, and a second level with a second die coupled to the first die. A third level includes a third die coupled to the second die. The levels have conductive first, second, and third interconnects, respectively, extending from active sides of the dies and may be bonded prior to stacking the dies. The dies may be stacked in an offset or rotated position relative to each other such that the interconnects extend beyond each of the other dies to contact a redistribution layer that forms electrical connections with external components. In some configurations, a fourth level having a fourth die and a conductive fourth interconnect is coupled to the third die and positioned laterally offset from the third die such that the third interconnect extends beyond the fourth die.

Abstract: A hybrid memory structure including a substrate, a flash memory, a first resistive random access memory (RRAM), and a second RRAM is provided. The flash memory is located on the substrate. The flash memory includes a gate, a first doped region, and a second doped region. The gate is located on the substrate. The first doped region is located in the substrate on one side of the gate. The second doped region is located in the substrate on another side of the gate. The first RRAM is electrically connected to one of the gate, the first doped region, and the second doped region. The second RRAM is electrically connected to another of the gate, the first doped region, and the second doped region.

Abstract: Methods and systems of detection of wafer de-chucking in a semiconductor processing chamber are disclosed. Methods and systems of interdiction are also disclosed to prevent hardware and wafer damage during semiconductor fabrication if and when de-chucking is detected. In one embodiment, a de-chucking detection method is based on measuring change in imaginary impedance of a plasma circuit, along with measuring one or both of reflected RF power and arc count. In another embodiment, a possibility of imminent de-chucking is detected even before complete de-chucking occurs by analyzing the signature change in imaginary impedance.

Abstract: A stacked quantum computing device including a first chip that includes a first dielectric substrate and a superconducting qubit on the first dielectric substrate, and a second chip that is bonded to the first chip and includes a second dielectric substrate, a qubit readout element on the second dielectric substrate, a control wire on the second dielectric substrate, a dielectric layer covering the control wire, and a shielding layer covering the dielectric layer.