Abstract: A pillar-shaped semiconductor memory device includes an i-layer substrate and silicon pillars formed on the i-layer substrate. Tunnel insulating layers, a data charge storage insulating layer, an interlayer insulating layer, and gas layers are formed so as to surround outer peripheries of the silicon pillars. Word lines that are separated from each other by interlayer insulating layers are formed so as to surround outer peripheries of the gas layers in a direction perpendicular to an upper surface of the i-layer substrate.

Abstract: A method includes forming one or more vias in a first layer, forming one or more vias in at least a second layer different than the first layer, aligning at least a first via in the first layer with at least a second via in the second layer, and bonding the first layer to the second layer by filling the first via and the second via with solder material using injection molded soldering.

Abstract: A device including a first semiconductor layer and a contact to the first semiconductor layer is disclosed. An interface between the first semiconductor layer and the contact includes a first roughness profile having a characteristic height and a characteristic width. The characteristic height can correspond to an average vertical distance between crests and adjacent valleys in the first roughness profile. The characteristic width can correspond to an average lateral distance between the crests and adjacent valleys in the first roughness profile.

Abstract: A method includes fabricating an image sensing element in a substrate. A plurality of inter-metal dielectric (IMD) layers are formed over the substrate. Each IMD layer includes a metal layer and a dielectric layer. A planar top surface of a top IMD layer of the plurality of IMD layers is planarized. A portion of the top IMD layer is then removed to transform a region of the planar top surface to a curved recess. A lens is formed on the top IMD layer and in the curved recess. A color filter layer is disposed over the lens and the image sensing element.

Abstract: An etch-stop annular spacer can be formed around a protruding portion of a sacrificial pillar structure that fills a lower memory opening through a first insulating cap layer and through an underlying first alternating stack of first insulating layers and first spacer layers. The etch-stop layer comprises a material that is different from the material of the sacrificial pillar structure. After formation of a second insulating cap layer, a second alternating stack of second insulating layers and second spacer layers can be formed over the sacrificial pillar structure. An upper memory opening is formed though the second alternating stack by an anisotropic etch that employs the etch-stop annular spacer as an etch stop. A memory opening is formed by removing the sacrificial pillar structure underneath the upper memory opening selective to the etch-stop annular spacer. A memory stack structure without a convex protrusion can be formed in the memory opening.

Abstract: A silicon germanium alloy (SiGe) fin having a first germanium content is provided within first and second device regions. Each SiGe fin is located on a sacrificial material stack and an oxide material surrounds each SiGe fin. A germanium layer is formed atop each SiGe fin within one of the device regions, while a SiGe layer having a second germanium content less than the first germanium content is formed atop each SiGe fin within the other device region. An exposed surface of each of the germanium layer and the SiGe layer is then bonded to a base substrate. The sacrificial material stack is removed and thereafter the oxide material is recessed to expose a portion of each SiGe fin in the first and second device regions. Each SiGe fin contacting the germanium layer compressively strained, and each SiGe fin contacting the SiGe layer is tensely strained.

Abstract: Semiconductor devices, FinFET devices and methods of forming the same are disclosed. In accordance with some embodiments, a semiconductor device includes a substrate, a first gate stack, a first dielectric layer, a shielding layer and a connector. The first gate stack is over a substrate. The first dielectric layer is aside the first gate stack, wherein the top surface of the first gate stack is lower than the top surface of the first dielectric layer such that a first recess is provided above the first gate stack. The shielding layer is on the surface of the first recess and extends onto the top surface of the first dielectric layer. The connector is through the shielding layer and is electrically connected to the first gate stack.

Abstract: A method includes forming one or more vias in a substrate, forming a first photoresist layer on a top surface of the substrate and a second photoresist layer on a bottom surface of the substrate, patterning the first photoresist layer and the second photoresist layer to remove at least a first portion of the first photoresist layer and at least a second portion of the second photoresist layer, filling the one or more vias, the first portion and the second portion with solder material using injection molded soldering, and removing remaining portions of the first photoresist layer and the second photoresist layer.

Abstract: Power gate placement techniques in three-dimensional (3D) integrated circuits (ICs) (3DICs) are disclosed. Exemplary aspects of the present disclosure contemplate consolidating power gating circuits or cells into a single tier within a 3DIC. Still further, the power gating circuits are consolidated in a tier closest to a voltage source. This closest tier may include a backside metal layer that allows a distance between the voltage source and the power gating circuits to be minimized. By minimizing the distance between the voltage source and the power gating circuits, power loss from routing elements therebetween is minimized. Further, by consolidating the power gating circuits in a single tier, routing distances between the power gating circuits and downstream elements may be minimized and power loss from those routing elements are minimized. Other advantages are likewise realized by placement of the power gating circuits according to exemplary aspects of the present disclosure.

Abstract: A semiconductor device in which a transistor using an oxide semiconductor containing In, Zn, or the like for a channel region can be driven like a p-channel transistor is provided. The semiconductor device includes a transistor and an inverter, wherein an output of the inverter is input to a gate of the transistor, a channel region of the transistor includes an oxide semiconductor film containing In, Zn, or Sn, and each channel region of transistors in the inverter contains silicon. When a high voltage is input to the inverter, a low voltage is output from the inverter and is input to the gate of the transistor, so that the transistor is turned off. When a low is input to the inverter, a high voltage is output from the inverter and is input to the gate of the transistor, so that the transistor is turned on.

Abstract: An angled gas cluster ion beam is used for each sidewall and top of a fin (two applications) to form work-function metal layer(s) only on the sidewalls and top of each fin.

Abstract: A semiconductor device including a semiconductor layer, a plurality of semiconductor fins formed on a surface of the semiconductor layer and a plurality of gate electrodes formed over the surface of the semiconductor layer is provided. The semiconductor fins extend in parallel to each other along a first direction parallel to the surface of the semiconductor layer and have a first height in a second direction that is perpendicular to the first direction, and the gate electrodes comprise longitudinal portions extending parallel to the semiconductor fins along the first direction and, in particular, having a second height in the second direction lower than the first height.

Abstract: A light emitting device includes an electrode layer, a first metal layer, an organic material layer and a second metal layer stacked sequentially. The first metal layer includes a first metal portion and a second metal portion separated from the first metal portion at a first lateral distance, and the first metal portion and the second metal portion have a first period. The organic material layer includes a first emitting region separating the first metal portion and the second metal portion. The first lateral distance and the first period enable a lateral plasma coupling generated between the first metal portion and the second metal portion, such that light generated by the organic material layer at the first emitting region has a gain in a first waveband, or a peak wavelength of the light generated by the first emitting region shifts to the first waveband.

Abstract: A semiconductor integrated circuit device may include a through silicon via (TSV), a keep out zone and a plurality of dummy patterns. The TSV may be arranged in a selection region of a semiconductor substrate. The keep out zone may be configured to define a peripheral region of the TSV. The dummy patterns may be arranged in the keep out zone to receive a conductive signal. The dummy patterns may function as an electrode of a reservoir capacitor.

Abstract: An electronic apparatus includes a semiconductor substrate and first and second transistors disposed in the semiconductor substrate. The first transistor includes a channel region and a drain region adjacent the channel region. The second transistor includes a channel region, a false drain region adjacent the channel region, and a drain region electrically coupled to the channel region by a drift region such that the second transistor is configured for operation at a higher voltage level than the first transistor. The respective channel regions of the first and second transistors have a common configuration characteristic.

Abstract: An organic light emitting diode (OLED) device includes a cathode, an anode and an organic function layer interposed between the cathode and the anode. A material of the cathode is at least one of a metal and a metal alloy. The light emitted from the organic function layer exits at least through the cathode. The organic light emitting diode device further includes an anti-reflective layer on a side of the cathode that faces away from the organic function layer. The anti-reflective layer includes a first surface and a second surface opposite to each other. The first surface contacts the cathode. External light reflected by the first surface and external light reflected by the second surface interfere destructively.

Abstract: A transistor device includes a compound semiconductor body, a drain disposed in the compound semiconductor body and a source disposed in the compound semiconductor body and spaced apart from the drain by a channel region. A gate is provided for controlling the channel region. The transistor device further includes a gate overvoltage protection device connected between the source and the gate, the gate overvoltage protection device including p-type and n-type silicon-containing semiconductor material.

Abstract: Transistors and methods of forming the same include forming a fin of alternating layers of a channel material and a sacrificial material. Stress liners are formed in contact with both ends of the fin. The stress liners exert a stress on the fin. The sacrificial material is etched away from the fin, such that the layers of the channel material are suspended between the stress liners. A gate stack is formed over and around the suspended layers of channel material.

Abstract: A resistive random access memory device and a method for fabricating the same are presented. The resistive random access memory device includes a first electrode having a first dopant within. A second electrode is disposed on the first electrode. A resistive switching layer is disposed between the first electrode and the second electrode.

Abstract: Embodiments of mechanisms for forming a semiconductor device are provided. The semiconductor device includes a semiconductor substrate and an isolation structure in the semiconductor substrate and surrounding an active region of the semiconductor substrate. The semiconductor device also includes a gate over the semiconductor substrate, and the gate has an intermediate portion over the active region and two end portions connected to the intermediate portion, and the end portions are over the isolation structure. The semiconductor device further includes a support film over the isolation structure and covering the isolation structure and at least one of the end portions of the gate. The support film exposes the active region and the intermediate portion of the gate.