Patents Examined by Jarrett Stark
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Patent number: 9728475Abstract: A miniaturized semiconductor device includes a frame body having an opening region formed in a central portion, an insulating substrate which is provided in the opening region of the frame body and on which semiconductor chips are mounted, lead portions, each including an inclined portion that is at least partially exposed to the opening region formed in the frame body and extends so as to be inclined with respect to an end surface forming the opening region, and a bonding wire that is bonded between the lead portion and the semiconductor chip by ultrasonic bonding.Type: GrantFiled: March 31, 2016Date of Patent: August 8, 2017Assignee: FUJI ELECTRIC CO., LTD.Inventors: Tadanori Yamada, Toshio Denta, Tomonori Seki
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Patent number: 9728626Abstract: A FinFET includes a fin and a conductive gate surrounding a top channel region of the fin, the channel region of the fin being filled with an epitaxial semiconductor channel material extending below a bottom surface of the conductive gate. The top channel region of the fin includes epitaxial semiconductor channel material that is at least majority defect free, the at least a majority of defects associated with forming the epitaxial semiconductor material in the channel region being trapped below a top portion of the channel region. The FinFET may be achieved by a method, the method including providing a starting semiconductor structure, the starting semiconductor structure including a bulk semiconductor substrate, semiconductor fin(s) on the bulk semiconductor substrate and surrounded by a dielectric layer, and a dummy gate over a channel region of the semiconductor fin(s).Type: GrantFiled: August 30, 2016Date of Patent: August 8, 2017Assignee: GLOBALFOUNDRIES INC.Inventors: Dominic J. Schepis, Charan V. Surisetty, Kangguo Cheng, Alexander Reznicek
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Patent number: 9721970Abstract: A method for manufacturing a fin field-effect transistor (FinFET) device, comprises patterning a first layer on a substrate to form at least one fin, patterning a second layer under the first layer to remove a portion of the second layer on sides of the at least one fin, forming a sacrificial gate electrode on the at least one fin, and a spacer on the sacrificial gate electrode, selectively removing the sacrificial gate electrode, depositing an oxide layer on top and side portions of the at least one fin corresponding to a channel region of the at least one fin, performing thermal oxidation to condense the at least one fin in the channel region until a bottom portion of the at least one fin is undercut, and stripping a resultant oxide layer from the thermal oxidation, leaving a gap in the channel region between a bottom portion of the at least one fin and the second layer.Type: GrantFiled: April 22, 2016Date of Patent: August 1, 2017Assignee: International Business Machines CorporationInventors: Karthik Balakrishnan, Kangguo Cheng, Pouya Hashemi, Alexander Reznicek
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Patent number: 9722076Abstract: A semiconductor device includes a substrate, two gate structures, an interlayer dielectric layer and a material layer. The substrate has at least two device regions separated by at least one isolation structure disposed in the substrate. Each device region includes two doped regions disposed in the substrate. The gate structures are respectively disposed on the device regions. In each device region, the doped regions are respectively disposed at two opposite sides of the gate structure. The interlayer dielectric layer is disposed over the substrate and peripherally surrounds the gate structures. A top of the interlayer dielectric layer has at least one concave. The material layer fills the concave and has a top surface elevated at the same level with top surfaces of the gate structures. A ratio of a thickness of a thickest portion of the material layer to a pitch of the gate structures ranges from 1/30 to 1/80.Type: GrantFiled: August 29, 2015Date of Patent: August 1, 2017Assignee: TAIWAN SEMICONDUCTOR MANUFACTURNING CO., LTD.Inventors: Chung-Ren Sun, Shiu-Ko Jangjian, Kun-Ei Chen, Chun-Che Lin
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Patent number: 9722081Abstract: A FinFET device and a method of forming the same are disclosed. In accordance with some embodiments, a FinFET device includes a substrate having at least one fin, a gate stack across the at least one fin, a strained layer aside the gate stack and a silicide layer over the strained layer. The strained layer has a boron surface concentration greater than about 2E20 atom/cm3 within a depth range of about 0-5 nm from a surface of the strained layer.Type: GrantFiled: January 29, 2016Date of Patent: August 1, 2017Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.Inventors: Chun Hsiung Tsai, Chien-Tai Chan, Ziwei Fang, Kei-Wei Chen, Huai-Tei Yang
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Patent number: 9722026Abstract: A semiconductor structure includes: a germanium layer; and a first insulating film that is formed on an upper surface of the germanium layer, primarily contains germanium oxide and a substance having an oxygen potential lower than an oxygen potential of germanium oxide, and has a physical film thickness of 3 nm or less; wherein a half width of frequency to height in a 1 ?m square area of the upper surface of the germanium layer is 0.7 nm or less.Type: GrantFiled: June 6, 2014Date of Patent: August 1, 2017Assignee: JAPAN SCIENCE AND TECHNOLOGY AGENCYInventors: Akira Toriumi, Toshiyuki Tabata, Choong Hyun Lee, Tomonori Nishimura, Cimang Lu
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Patent number: 9722048Abstract: A semiconductor device includes a source including a first doped semiconductor layer arranged on a substrate, a layer of metal arranged on the first doped semiconductor layer, and a second doped semiconductor layer arranged on the layer of metal; a channel extending from the second doped semiconductor layer to a drain including an epitaxial growth; a gate disposed on sidewalls of the channel between the second doped semiconductor layer and the drain; an interlayer dielectric (ILD) disposed on the second doped semiconductor layer and the gate; and a source contact extending from a surface of the ILD to abut the layer of metal of the source.Type: GrantFiled: March 28, 2016Date of Patent: August 1, 2017Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATIONInventors: Karthik Balakrishnan, Kangguo Cheng, Pouya Hashemi, Alexander Reznicek
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Patent number: 9721833Abstract: A semiconductor device with voids within a silicon-on-insulator (SOI) structure and a method of forming the semiconductor device are provided. Voids are formed within a Buried Oxide layer (BOX layer) of the silicon-on-insulator (SOI) semiconductor to enhance a performance index of an RF-SOI switch. The semiconductor device with voids within a silicon-on-insulator (SOI) structure includes a semiconductor substrate; an insulating layer disposed on the substrate; a silicon-on-insulator (SOI) layer disposed on the insulating layer; a device isolation layer and an active area disposed within the SOI layer; one or more voids disposed within the insulating layer; and a sealing insulating sealing an opening of the void.Type: GrantFiled: May 13, 2016Date of Patent: August 1, 2017Assignee: Magnachip Semiconductor, Ltd.Inventor: Francois Hebert
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Patent number: 9722086Abstract: In a logic circuit where clock gating is performed, the standby power is reduced or malfunction is suppressed. The logic circuit includes a transistor which is in an off state where a potential difference exists between a source terminal and a drain terminal over a period during which a clock signal is not supplied. A channel formation region of the transistor is formed using an oxide semiconductor in which the hydrogen concentration is reduced. Specifically, the hydrogen concentration of the oxide semiconductor is 5×1019 (atoms/cm3) or lower. Thus, leakage current of the transistor can be reduced. As a result, in the logic circuit, reduction in standby power and suppression of malfunction can be achieved.Type: GrantFiled: February 8, 2013Date of Patent: August 1, 2017Assignee: Semiconductor Energy Laboratory Co., Ltd.Inventors: Yutaka Shionoiri, Hidetomo Kobayashi
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Patent number: 9716063Abstract: A pattern is provided in a dielectric layer in which a set of features are patterned for a set of metal conductor structures. An adhesion promoting layer is created disposed over the patterned dielectric. A metal layer is deposited to fill a first portion of the set of features disposed the adhesion promoting layer. A ruthenium layer is deposited disposed over the metal layer. Using a physical vapor deposition process, a cobalt layer is deposited disposed over the ruthenium layer. A thermal anneal reflows the cobalt layer to fill a second portion of the set of features. In another aspect of the invention, a device created by the method is described.Type: GrantFiled: August 17, 2016Date of Patent: July 25, 2017Assignee: International Business Machines CorporationInventors: Daniel C Edelstein, Chih-Chao Yang
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Patent number: 9716092Abstract: A semiconductor device employs surrounding gate transistors (SGTs) which are vertical transistors to constitute a CMOS NAND circuit. The NAND circuit is formed by using a plurality of MOS transistors arranged in m rows and n columns. The MOS transistors constituting the NAND circuit are formed on a planar silicon layer disposed on a substrate, and each have a structure in which a drain, a gate, and a source are arranged in a vertical direction, the gate surrounding a silicon pillar. The planar silicon layer includes a first active region having a first conductivity type and a second active region having a second conductivity type. The first active region and the second active region are connected to one another via a silicon layer formed on a surface of the planar silicon layer. This provides for a semiconductor device that constitutes a NAND circuit.Type: GrantFiled: October 27, 2016Date of Patent: July 25, 2017Assignee: Unisantis Electronics Singapore Pte. Ltd.Inventors: Fujio Masuoka, Masamichi Asano
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Patent number: 9716067Abstract: Embodiments of the present disclosure are directed towards an integrated circuit (IC) package having first and second dies with first and second input/output (I/O) interconnect structures, respectively. The IC package may include a bridge having first and second electrical routing features coupled to a portion of the first and second I/O interconnect structures, respectively. In embodiments, the first and second electrical routing features may be disposed on one side of the bridge; and third electrical routing features may be disposed on an opposite side. The first and second electrical routing features may be configured to route electrical signals between the first die and the second die and the third electrical routing features may be configured to route electrical signals between the one side and the opposite side. The first die, the second die, and the bridge may be embedded in electrically insulating material. Other embodiments may be described and/or claimed.Type: GrantFiled: January 22, 2016Date of Patent: July 25, 2017Assignee: Intel CorporationInventors: Ravindranath V. Mahajan, Christopher J. Nelson, Omkar G. Karhade, Feras Eid, Nitin A. Deshpande, Shawna M. Liff
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Patent number: 9711697Abstract: According to one aspect, the present invention concerns a terahertz modulator (1) intended to be used in a given frequency band of use. The modulator comprises a semi-conductor polar crystal (330) presenting a Reststrahlen band overlapping said frequency band of use and presenting at least one interface with a dielectric medium, coupling means (330) allowing the resanant coupling of an interface phonon polariton (IPhP) supported by said interface and of an incident radiation (2) of pre-determined frequency lying in said frequency band of use and means of control (22) apt to modify the intensity of the coupling between said interface phonon polariton and said incident radiation (2) by modification of the dielectric function of the polar crystal in the Reststrahlen band of the polar crystal (10).Type: GrantFiled: February 14, 2012Date of Patent: July 18, 2017Assignee: Centre National de la Recherche Scientifique—CNRSInventors: Simon Vassant, Fabrice Pardo, Jean-Luc Pelouard, Jean-Jacques Greffet, Alexandre Archambault, François Marquier
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Patent number: 9711607Abstract: A method and structure for providing a GAA device. In some embodiments, a substrate including an insulating layer disposed thereon is provided. By way of example, a first metal portion is formed within the insulating layer. In various embodiments, a first lateral surface of the first metal portion is exposed. After exposure of the first lateral surface of the first metal portion, a first graphene layer is formed on the exposed first lateral surface. In some embodiments, the first graphene layer defines a first vertical plane parallel to the exposed first lateral surface. Thereafter, in some embodiments, a first nanobar is formed on the first graphene layer, where the first nanobar extends in a first direction normal to the first vertical plane defined by the first graphene layer.Type: GrantFiled: April 15, 2016Date of Patent: July 18, 2017Assignees: Taiwan Semiconductor Manufacturing Co., Ltd., National Taiwan UniversityInventors: Che-Wei Yang, Chi-Wen Liu, Hao-Hsiung Lin, Ling-Yen Yeh
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Patent number: 9711618Abstract: A method of forming a gate structure, including forming one or more vertical fins on a substrate; forming a bottom spacer on the substrate surface adjacent to the one or more vertical fins; forming a gate structure on at least a portion of the sidewalls of the one or more vertical fins; forming a gauge layer on at least a portion of the bottom spacer, wherein the gauge layer covers at least a portion of the gate structure on the sidewalls of the one or more vertical fins; and removing a portion of the gauge layer on the bottom spacer.Type: GrantFiled: March 31, 2016Date of Patent: July 18, 2017Assignee: International Business Machines CorporationInventors: Kangguo Cheng, Ruilong Xie, Tenko Yamashita, Chun-Chen Yeh
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Patent number: 9711433Abstract: A semiconductor device includes: a first semiconductor element; a first substrate provided on the first semiconductor element and including a cavity with reduced pressure; coolant held inside the cavity; a second semiconductor element provided on the first substrate; and a heat spreading member thermally connected to the first substrate and provided with a hole communicated with the cavity.Type: GrantFiled: November 3, 2015Date of Patent: July 18, 2017Assignee: FUJITSU LIMITEDInventors: Jun Taniguchi, Takeshi Shioga, Yoshihiro Mizuno
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Patent number: 9711634Abstract: A super junction MOSFET includes a parallel pn layer including a plurality of pn junctions and in which an n-type drift region and a p-type partition region interposed between the pn junctions are alternately arranged and contact each other, a MOS gate structure on the surface of the parallel pn layer, and an n-type buffer layer in contact with an opposite main surface. The impurity concentration of the buffer layer is equal to or less than that of the n-type drift region. At least one of the p-type partition regions in the parallel pn layer is replaced with an n? region with a lower impurity concentration than the n-type drift region. With this structure, it is possible to provide a super junction MOSFET which prevents a sharp rise in hard recovery waveform during a reverse recovery operation.Type: GrantFiled: October 13, 2015Date of Patent: July 18, 2017Assignee: FUJI ELECTRIC CO., LTD.Inventors: Takahiro Tamura, Yasuhiko Onishi
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Patent number: 9711683Abstract: The present application discloses a semiconductor device comprising a crystalline substrate having a first region and a second region, a nuclei structure on the first region, a first crystalline buffer layer on the nuclei structure, a void between the second region and the first crystalline buffer layer, a second crystalline buffer layer on the first crystalline buffer layer, an intermediate layer located between the first crystalline buffer layer and the second crystalline buffer layer, and a semiconductor device layer on the second crystalline buffer layer.Type: GrantFiled: September 26, 2014Date of Patent: July 18, 2017Assignee: EPISTAR CORPORATIONInventors: Heng-Kuang Lin, Ya-Yu Yang
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Patent number: 9711613Abstract: In an aspect of the present invention, a graphene field-effect transistor (GFET) structure is formed. The GFET structure comprises a wider portion and a narrow extension portion extending from the wider portion that includes one or more graphene layers edge contacted to source and drain contacts, wherein the source and drain contacts are self-aligned to the one or more graphene layers.Type: GrantFiled: November 3, 2016Date of Patent: July 18, 2017Assignee: International Business Machines CorporationInventors: Aaron D. Franklin, Hiroyuki Miyazoe, Satoshi Oida, Joshua T. Smith
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Patent number: 9711621Abstract: A trench transistor having a semiconductor body includes a source region, a body region, a drain region electrically connected to a drain contact, and a gate trench including a gate electrode which is isolated from the semiconductor body. The gate electrode is configured to control current flow between the source region and the drain region along at least a first side wall of the gate trench. The trench transistor further includes a doped semiconductor region having dopants introduced into the semiconductor body through an unmasked part of the walls of a trench.Type: GrantFiled: July 30, 2014Date of Patent: July 18, 2017Assignee: Infineon Technologies AGInventors: Franz Hirler, Uwe Wahl, Thorsten Meyer, Michael Rüb, Armin Willmeroth, Markus Schmitt, Carolin Tolksdorf, Carsten Schaeffer