Abstract: The present invention provides a manufacturing method of a device embedded substrate, including: forming a bonding layer of an insulation material on a metal layer formed on a support plate; and mounting an electric or electronic device on the bonding layer, wherein the device is formed of a device main body and a protruding terminal; the bonding layer includes a first bonding body bonded with the metal layer and a second bonding body bonded with the device; the first bonding body is formed along the outer edge of the device; the second bonding body is formed in an area equal or smaller than the area defined by the outer edge of the terminal; and, in the bonding layer forming step, the second bonding body is formed on the first bonding body after the first bonding body is cured.

Abstract: A substrate for mounting a semiconductor includes a first insulation layer having first and second surfaces on the opposite sides and having a penetrating hole penetrating through the first insulation layer, an electrode formed in the penetrating hole in the first insulation layer and having a protruding portion protruding from the second surface of the first insulation layer, a first conductive pattern formed on the first surface of the first insulation layer and connected to the electrode, a second insulation layer formed on the first surface of the first insulation layer and the first conductive pattern and having a penetrating hole penetrating through the second insulating layer, a second conductive pattern formed on the second insulation layer and for mounting a semiconductor element, and a via conductor formed in the penetrating hole in the second insulation layer and connecting the first and second conductive patterns.

Abstract: A semiconductor device is disclosed. The semiconductor device has a semiconductor chip, an island having an upper surface to which the semiconductor chip is bonded, a lead disposed around the island, a bonding wire extended between the surface of the semiconductor chip and the upper surface of the lead, and a resin package sealing the semiconductor chip, the island, the lead, and the bonding wire, while the lower surface of the island and the lower surface of the lead are exposed on the rear surface of the resin package, and the lead is provided with a recess concaved from the lower surface side and opened on a side surface thereof.

Abstract: Provided is a method for manufacturing an organic EL device which suppresses a deterioration in the light emission properties. In this method, while first and second electrode layers are prevented from being in contact with each other, an organic layer is allowed to protrude from the first electrode layer toward at least both outer sides in the longitudinal direction of a substrate. Further, the second electrode layer is allowed to protrude from the organic layer toward at least both outer sides in the longitudinal direction. Thereby, the first electrode layer, the organic layer, and the second electrode layer are formed so that both end edges of the organic layer in a longitudinal direction of the substrate are covered by both end sides of the second electrode layer in the longitudinal direction, on at least both outer sides of the light emitting part in the longitudinal direction.

Abstract: The present invention relates to a method for forming a copper pillar on a semiconducting substrate, the copper pillar having an underbump metallization area comprising a metal less noble than copper and optionally a solder bump on the top portion, and having a layer of a second metal selected from tin, tin alloys, silver, and silver alloys deposited onto the side walls of said copper pillar. A layer of a first metal which is more noble than copper is deposited onto the entire outer surface of the copper pillar prior to deposition of the second metal layer. The layer of a second metal then has at least a reduced number of undesired pin-holes and serves as a protection layer for the underlying copper pillar.

Abstract: In a semiconductor device, a conductor pattern is disposed in a position overlapped by a semiconductor chip in a thickness direction over the mounting surface (lower surface) of a wiring board. A solder resist film (insulating layer) covering the lower surface of the wiring board has apertures formed such that multiple portions of the conductor pattern are exposed. The conductor pattern has conductor apertures. The outlines of the apertures and the conductor apertures overlap with each other, in a plan view, respectively.

Abstract: A semiconductor module system has a semiconductor module and a protective cover. The semiconductor module has a bottom side with a heat dissipation surface and a top side opposite the bottom side, the top side being separated from the bottom side in a vertical direction. The protective cover can be mounted irreleasably on the semiconductor module in such a way that, in a mounted state, the top side is exposed and the protective cover covers the heat dissipation surface. By virtue of the protective cover, a thermal interface material applied onto the heat dissipation surface can be protected.

Abstract: There is provided a semiconductor device having a converter circuit, a brake circuit and an inverter circuit and manufacturable by a simplified manufacturing process. The semiconductor device has a plurality of die pads, IGBTs, diodes, freewheel diodes, an HVIC and LVICs mounted on the plurality of die pads, a plurality of leads, and an encapsulation resin body that covers these component parts. In a manufacturing process, a single-plate lead frame having the above-described plurality of die pads and leads connected together can be prepared. The semiconductor device may be manufactured by using this single-plate lead frame.

Abstract: A semiconductor device manufacturing method includes: a first-process for placing, on a first-substrate on which traces and first-electrodes are formed, each of the first-electrodes being connected to one of traces, a second-substrate in which through-holes corresponding to the first-electrodes and relay-members are disposed, each of the relay-members being formed of solder, penetrating through one of the through-holes, and projecting from both ends of the one of the through-holes, so that the first-electrodes are aligned with the through-holes in a plan view; a second-process for melting the relay-members so that the relay-members are connected to the first-electrodes, after the first-process; and a third-process for placing a semiconductor substrate on which a second-electrodes corresponding to the first-electrodes are formed on a side opposite to the first-substrate across the second-substrate, after the second-process, to connect the first-electrodes and the second-electrodes to each other via the relay-m

Abstract: An aligning guide, a semiconductor package comprising an aligning guide, and a method of manufacturing a semiconductor package comprising an aligning guide are provided. The semiconductor package may comprise a circuit board and an aligning guide mounted on the circuit board. The aligning guide may have a plurality of stepped portions. A plurality of semiconductor chips may be stacked on the circuit board and engage with the stepped portions of the aligning guide. According to the disclosed semiconductor package, a large number of semiconductor chips may be stacked with high accuracy and sufficient margin. Therefore, the rate of failure and defects in the chip stacking process may be reduced and the reliability and stability of the semiconductor package may be enhanced.

Abstract: An embodiment of an electronic assembly for mounting on an electronic board includes a plurality of electric contact regions exposed on a mounting surface of the electronic board. The electronic assembly includes a chip of semiconductor material in which at least one electronic component is integrated, at least one support element including a first main surface and a second main surface opposite to the first main surface, the chip being enclosed by the at least one support element, a heat dissipation plate thermally coupled to said chip to dissipate the heat produced by it, exposed on the first main surface of the support element, a plurality of contact elements, each electrically coupled to a respective electric terminal of the electronic component integrated in the chip, exposed on the same first main surface of which is exposed to the dissipation plate.

Abstract: A method for fabrication a metal pillar bump packaging structure is provided. The method includes providing a semiconductor substrate; and forming a metal interconnect structure and a dielectric layer exposing a portion of the metal interconnect structure on the semiconductor substrate. The method also includes forming a photoresist layer having an opening with an undercut with a bottom area greater than a top area at the bottom of the opening to expose the metal interconnect structure and a portion of the dielectric layer on the semiconductor substrate; and forming a metal pillar bump structure having a pillar body and an extension part with an enlarged bottom area in the opening and the undercut. Further, the method includes forming a soldering ball on the metal pillar bump structure.

Abstract: A method of forming a semiconductor device package includes bonding a first connector to a first conductive structure on a first package. The method includes bonding a die to a surface of the first package, wherein a top surface of the first connector extends above a top surface of the die. The method includes surrounding the first connector with a molding compound. The method includes removing a portion of the first connector and a portion of the molding compound. The top surface of the remaining first conductor is below the top surface of the die. A first top surface of the remaining molding compound is below the top surface of the die. A second top surface of the remaining molding compound is level with the top surface of the die. The method includes bonding a second connector to the remaining portion of the first connector.

Abstract: A microelectronic package can include a substrate having first and second opposed surfaces extending in first and second transverse directions and an opening extending between the first and second surfaces and defining first and second distinct parts each elongated along a common axis extending in the first direction, first and second microelectronic elements each having a front surface facing the first surface of the substrate and a column of contacts at the respective front surface, a plurality of terminals exposed at the second surface, and first and second electrical connections aligned with the respective first and second parts of the opening and extending from at least some of the contacts of the respective first and second microelectronic elements to at least some of the terminals. The column of contacts of the first and second microelectronic elements can be aligned with the respective first and second parts of the opening.

Abstract: A wafer level array of chips is provided. The wafer level array of chips comprises a semiconductor wafer, and a least one extending-line protection. The semiconductor wafer has at least two chips, which are arranged adjacent to each other, and a carrier layer. Each chip has an upper surface and a lower surface, and comprises at least one device. The device is disposed upon the upper surface, covered by the carrier layer. The extending-line protection is disposed under the carrier layer and between those two chips. The thickness of the extending-line protection is less than that of the chip. Wherein the extending-line protection has at least one extending-line therein. In addition, a chip package fabricated by the wafer level array of chips, and a method thereof are also provided.

Abstract: A semiconductor device has a semiconductor die and first insulating layer formed over the semiconductor die. A patterned trench is formed in the first insulating layer. A conductive ink is deposited in the patterned trench by disposing a stencil over the first insulating layer with an opening aligned with the patterned trench and depositing the conductive ink through the opening in the stencil into the patterned trench. Alternatively, the conductive ink is deposited by dispensing the conductive ink through a nozzle into the patterned trench. The conductive ink is cured by ultraviolet light at room temperature. A second insulating layer is formed over the first insulating layer and conductive ink. An interconnect structure is formed over the conductive ink. An encapsulant can be deposited around the semiconductor die. The patterned trench is formed in the encapsulant and the conductive ink is deposited in the patterned trench in the encapsulant.

Abstract: A wiring substrate includes a first multi-layer wiring layer including an insulating layer formed of a non-photosensitive resin, a plurality of external connection pads formed on an upper face side of the first multi-layer wiring layer, and a second multi-layer wiring layer formed on the first multi-layer wiring layer, the second multi-layer wiring layer including an insulating layer formed of a photosensitive resin, the second multi-layer wiring layer having a wiring pitch narrower than the wiring pitch of the first multi-layer wiring layer. The external connection pads are exposed from the insulating layer of the second multi-layer wiring layer.

Abstract: A device includes a substrate having a base member and an insulation film formed on a surface of the base member, a first semiconductor chip mounted over a surface of the substrate on which the insulation film are formed, a second semiconductor chip stacked over the first semiconductor chip so that an overhang portion is formed, and a sealing member formed on the substrate so that the first semiconductor chip and the second semiconductor chip are covered with the sealing member. The insulation film has a first opening portion in a first area of the substrate that overlaps the overhang portion. The base member has an air passage communicating with the first opening portion.

Abstract: A method of manufacturing an electronic device in which an inner space for housing a gyro element is formed between a base and a lid and the base and the lid are bonded includes bonding the base and the lid in which a groove is provided on a surface to be bonded with the base so that the inner space communicates with the outside by not bonding the inner surface of the groove to the base and to position the groove around a concave portion provided on a side surface of the base, and closing a communication portion by irradiating a laser beam to the lid in the communication portion.

Abstract: An embodiment device package includes a fan-out redistribution layer (RDL), a device over and bonded to the fan-out RDL, and a molding compound over the fan-out RDL and extending along sidewalls of the device. The device includes a first functional tier having a first metallization layer and a second functional tier having a second metallization layer. The second functional tier is bonded to the first functional tier. The device further includes an interconnect structure electrically connecting the first metallization layer to the second metallization layer. The interconnect structure includes an inter-tier via (ITV) at least partially disposed in both the first functional tier and the second functional tier, and the ITV contacts the first metallization layer.