Abstract: Dies having alignment marks and methods of forming the same are provided. A method includes forming trenches on a first side of a first workpiece, a die of the first workpiece being interposed between neighboring trenches. A portion of the die is removed to form an alignment mark, the alignment mark extending through an entire thickness of the die. A second side of the first workpiece is thinned until the die is singulated, the second side being opposite the first side.

Abstract: A light-emitting diode (LED) includes a first type semiconductor layer, a second type semiconductor layer, a first current controlling structure, and a first electrode. The second type semiconductor layer is joined with the first type semiconductor layer. The second type semiconductor layer has a first region and a second region, in which the first region has a first threading dislocation density, the second region has a second threading dislocation density, and the first threading dislocation density is greater than the second threading dislocation density. The first current controlling structure is joined with the first type semiconductor layer and has at least one first current-injecting zone therein, in which the vertical projection of the second region on the first current controlling structure at least partially overlaps with the first current-injecting zone. The first electrode is electrically coupled with the first type semiconductor layer.

Abstract: An integrated circuit packaging system, and a method of manufacture thereof, includes: an embedded trace substrate having bonding sites and traces embedded in a base material, an insulation layer on the traces, the insulation layer having a top surface coplanar with the top surface of the base material; and an integrated circuit die connected to the bonding sites.

Abstract: Provided is a method of mounting a chip. The method includes: forming a bump at one surface of a cavity formed concavely in an inner direction of a substrate; performing a coining process to flatten a surface of the bump; coating a solder material on the bump subjected to the coining process; and bonding a chip and the bump by melting the solder material, wherein an electrode portion or a metal portion is formed on a bottom of the chip. For a metal substrate according to the present invention, wherein a vertical insulating layer is included, since the electrode portion of the chip and the electrode portion of the substrate have to be electrically connected, the metal substrate is bonded to the electrode portion of the chip using the bump additionally formed on the metal substrate, so the heat generated in the chip can be rapidly transferred to the substrate, and the junction temperature of the chip can be decreased, thereby enhancing the light efficiency and the.

Abstract: A memory card has a wiring board, four memory chips stacked on a main surface of the wiring board, and a controller chip and an interposer mounted on a surface of the memory chip of the uppermost layer. The memory chips are stacked on the surface of the wiring board so that their long sides are directed in the same direction as that of the long side of the wiring board. The memory chip of the lowermost layer is mounted on the wiring board in a dislocated manner by a predetermined distance in a direction toward a front end of the memory card so as not to overlap the pads of the wiring board. The three memory chips stacked on the memory chip of the lowermost layer are disposed so that their short sides on which pads are formed are located at the front end of the memory card.

Abstract: The present invention provides a method for manufacturing a semiconductor structure, comprising: a) forming metal interconnect liners on a substrate; b) forming a mask layer to cover the metal interconnect liners and forming openings, which expose the metal interconnect liners, on the mask layer; c) etching and disconnecting the metal interconnect liners via the openings, thereby insulating and isolating the metal interconnect liners. The present invention further provides a semiconductor structure, which comprises a substrate and metal interconnect liners, wherein ends of the metal interconnect liners are disconnected by insulating walls formed within the substrate. The structure and the method provided by the present invention are favorable for shortening distance between ends of adjacent metal interconnect liners, saving device area and suppressing short circuits happening to metal interconnect liners.

Abstract: A method and apparatus for a conductive pillar structure is provided. A device may be provided, which may include a substrate, a first passivation layer formed over the substrate, a conductive interconnect extending through the first passivation layer and into the substrate, a conductive pad formed over the first passivation layer, and a second passivation layer formed over the interconnect pad and the second passivation layer. A portion of the interconnect pad may be exposed from the second passivation layer. The conductive pillar may be formed directly over the interconnect pad using one or more electroless plating processes. The conductive pillar may have a first and a second width and a first height corresponding to a distance between the first width and the second width.

Abstract: The present disclosure relates to a semiconductor substrate, a semiconductor package structure, and methods for making the same. A method includes providing a substrate and a carrier layer. The substrate includes a first patterned metal layer, a second patterned metal layer spaced from the first patterned metal layer, and a dielectric layer disposed between the first patterned metal layer and the second patterned metal layer. The dielectric layer covers the second patterned metal layer. The dielectric layer defines first openings exposing the second patterned metal layer, and further defines a via opening extending from the first patterned metal layer to the second patterned metal layer. A conductive material is disposed in the via and electrically connects the first patterned metal layer to the second patterned metal layer. The carrier layer defines second openings exposing the second patterned metal layer.

Abstract: Die packages and method of manufacturing the same are disclosed. In an embodiment, a method of manufacturing a die package may include forming an encapsulated via structure including at least one via, a polymer layer encapsulating the at least one via, and a first molding compound encapsulating the polymer layer; placing the encapsulated via structure and a first die stack over a carrier, the at least one via having a first end proximal the carrier and a second end distal the carrier; encapsulating the first die stack and the encapsulated via structure in a second molding compound; and forming a first redistribution layer (RDL) over the second molding compound, the first RDL electrically connecting the at least one via.

Abstract: The present invention provides a chip package that includes a semiconductor chip, at least one recess, a plurality of first redistribution metal lines, and at least one protrusion. The semiconductor chip has a plurality of conductive pads disposed on an upper surface of the semiconductor chip. The recess extends from the upper surface to a lower surface of the semiconductor chip, and is arranged on the side of the semiconductor chip. The first redistribution metal lines are disposed on the upper surface, electrically connected to the conductive pad individually, and extended into the recesses separately. The protrusion is disposed in the recess and located between the adjacent first redistribution metal lines.

Abstract: A semiconductor apparatus has a configuration in which multiple copper wiring layers and multiple insulating layers are alternately layered. A low-impedance wiring is formed occupying a predetermined region. A first wiring pattern includes multiple copper wiring members arranged in parallel with predetermined intervals in a first copper wiring layer, each of which has a rectangular shape extending in a first direction. A second wiring pattern includes multiple copper wiring members arranged in parallel with predetermined intervals in a second copper wiring layer adjacent to the first copper wiring layer, each of which has a rectangular shape extending in a second direction orthogonal to the first direction. The region occupied by the first wiring pattern and that occupied by the second wiring pattern are arranged such that they at least overlap. The first wiring pattern and the second wiring pattern are electrically connected so as to have the same electric potential.

Abstract: An electronic component includes a plurality of electrodes provided in a rectangular or substantially rectangular box-shaped area on an upper surface of a substrate, an electronic component element mounted on the substrate by flip-chip bonding, and an identification mark. The identification mark is provided between a first electrode, which is arranged along one side of the rectangular or substantially rectangular box-shaped area, and a second electrode, which is adjacent to the first electrode along the one side, of the plurality of electrodes provided on the upper surface of the substrate, and is located on or outside a line connecting the outer side edges of the first and second electrodes.

Abstract: A method for producing a micromechanical component, and a micromechanical component, includes providing a substrate having first and second outer surfaces, the second surface facing away from the first surface; forming a through-hole through the substrate from the first outer surface up to the second outer surface; attaching an optical functional layer, on the second outer surface, to cover the through-hole; removing a first segment of the substrate on the first surface of the substrate so that there arises a third outer surface inclined relative to the second surface, the third surface facing away from the second surface, the inclined surface enclosing the through-hole; and separating the micromechanical component by separating a first part of the substrate, having the through-hole, and a second part, attached to the first part, of the optical functional layer from a remaining part of the substrate and a remaining part of the optical functional layer.

Abstract: Embodiments of the present disclosure provide a package comprising a die attach pad, a die disposed on the die attach pad and a leadframe. The leadframe includes an opening defined therein that exposes a bottom surface of the die attach pad. The leadframe comprises a plurality of bond pads that are exposed at a bottom surface of the leadframe and a plurality of traces that are exposed at the bottom surface of the leadframe. Each trace of the plurality of traces is coupled to a corresponding bond pad of the plurality of bond pads. At least some of the traces are coupled to the die at top surfaces of the at least some of the traces. The leadframe also comprises a plurality of first insulated barriers. Each first insulated barrier is located between (i) a corresponding trace and (ii) a corresponding bond pad coupled to the corresponding trace.

Abstract: Various methods and devices that involve phase change material (PCM) switches are disclosed. An exemplary integrated circuit comprises an active layer with a plurality of field effect transistor (FET) channels for a plurality of FETs. The integrated circuit also comprises an interconnect layer comprising a plurality of conductive interconnects. The plurality of conductive interconnects couple the plurality of field effect transistors. The integrated circuit also comprises an insulator layer covering at least a portion of the interconnect layer. The integrated circuit also comprises a channel of a radio-frequency (RF) PCM switch. The channel of the RF PCM switch is formed on the insulator layer.

Abstract: A method of ultrasonically bonding semiconductor elements includes the steps of: (a) aligning surfaces of a plurality of first conductive structures of a first semiconductor element to respective surfaces of a plurality of second conductive structures of a second semiconductor element, wherein the surfaces of each of the plurality of first conductive structures and the plurality of second conductive structures include aluminum; and (b) ultrasonically bonding ones of the first conductive structures to respective ones of the second conductive structures.

Abstract: A wire bonding method includes the following steps. First, a substrate including at least one metal finger is provided. Next, a first chip including at least one first boding pad is disposed on the substrate. Next, a metal ball bump is formed on the corresponding metal finger. Next, a first wire is formed from the metal ball bump toward the corresponding first boding pad. Next, a first free air ball is formed on the first wire by electronic flame-off process. Then, the first free air ball connected to the first wire is pressed on the corresponding first boding pad, such that the first wire is located between the first free air ball and the corresponding first boding pad. A package structure using the wire bonding method is also provided.

Abstract: An interconnect structure and a method of forming an interconnect structure are disclosed. The interconnect structure includes a lower conductive feature in a lower low-k (LK) dielectric layer; a first etch stop layer (ESL) over the lower conductive feature, wherein the first ESL comprises a metal compound; an upper LK dielectric layer over the first ESL; and an upper conductive feature in the upper LK dielectric layer, wherein the upper conductive feature extends through the first ESL and connected to the lower conductive feature. The interconnect structure may further include a second ESL between the upper LK dielectric layer and the first ESL, or between the first ESL and the lower conductive feature, wherein the second ESL comprises a silicon compound.

Abstract: A semiconductor device may include an enclosure structure. The semiconductor device may further include a getter for absorb gas molecules. The getter may be positioned (and enclosed) inside the enclosure structure and may overlap a first portion of a surface of the enclosure structure. The semiconductor device may further include an inductor. The inductor may be positioned (and enclosed) inside the enclosure structure and may overlap a second portion of the surface of the enclosure structure without overlapping the getter in a direction perpendicular to the first surface of the enclosure structure.

Abstract: A semiconductor device has a semiconductor element provided with a functional surface on which a functional circuit is formed and with a back surface facing in the opposite direction to the functional surface, while also having a lead supporting the semiconductor element and electrically connected to the semiconductor element, and a resin package covering at least a portion of the semiconductor element and the lead. The semiconductor element has a functional surface side electrode formed on the functional surface and equipped with a functional surface side raised part that projects in the direction in which the functional surface faces. The functional surface side raised part of the functional surface side electrode is joined to the lead by solid state bonding.