Abstract: An integrated circuit structure includes an alignment bump and an active electrical connector. The alignment bump includes a first non-solder metallic bump. The first non-solder metallic bump forms a ring encircling an opening therein. The active electrical connector includes a second non-solder metallic bump. A surface of the first non-solder metallic bump and a surface of the second non-solder metallic bump are substantially coplanar with each other.

Abstract: Embodiments of the invention comprise a homogeneous heat spreading cap element in chip packages to facilitate better heat spreading and dissipation. The heat spreading cap comprises a single high-K graphite layer supported by a copper frame for increased stability and reduced thermal warpage during handling and operation while minimizing thermal penalty by reducing the amount of material having a relatively low heat conductivity that is needed in conventional heat spreading caps.

Abstract: A semiconductor apparatus is provided. The semiconductor apparatus includes: a base having a main surface on which a terminal is disposed; a first semiconductor device retained on the main surface of the base and having a top surface on which an electrode is disposed and a bottom surface facing the main surface of the base; a connection member connecting the terminal and the electrode; an encapsulant disposed on the main surface of the base and covering the terminal, the first semiconductor device and the connection member; and a heat dissipating member disposed on the encapsulant and having a space that opens in a direction extending perpendicular to the main surface of the base. The encapsulant is disposed in the space and, in a side view of the base, a peak of the connection member is located inside the space.

Abstract: An interconnect structure is provided that may include at least one cured permanent patterned dielectric material located on a surface of a substrate. The at least one cured permanent patterned dielectric material is a cured product of a patterned photoresist that includes a dielectric enabling element therein. The structure further includes at least one conductively filled region embedded within the at least one cured permanent patterned dielectric material.

Abstract: A semiconductor package comprising: a semiconductor chip comprising a first surface on a first side of the semiconductor chip and a second surface on a second side of the semiconductor chip, wherein the first side and the second side are opposite sides of the semiconductor chip; a through-electrode penetrating the semiconductor chip between the first surface and the second surface; a passivation layer formed on the second surface of the semiconductor chip; and an electrode pad formed on an upper surface of the passivation layer and electrically connected to the through-electrode, wherein the passivation layer comprises a first passivation layer formed on the second surface of the semiconductor chip and a second passivation layer formed on an upper surface of the first passivation layer, and the electrode pad penetrates the second passivation layer to contact the upper surface of the first passivation layer.

Abstract: A method for treating a chip packaging structure includes providing a chip packaging structure having at least a first electrical connect structure and a second electrical connect structure, and an insulation layer exposing portions of the first electrical connect structure and the second electrical connect structure; selecting a plasma gas based on materials of the first electrical connect structure and the second electrical connect structure and a type of process forming the first electrical connect structure and the second electrical connect structure, wherein metal cations are left on the insulation layer; performing a plasma treatment process using the selected plasma gas on the first electrical connect structure, the second electrical connect structure and the insulation layer, causing reaction of the metal cations to substantially convert the metal cations into electrically neutral materials; and removing the reacted metal cations from the insulation layer.

Abstract: A method for manufacturing semiconductor device may include the following steps: performing an etching process to remove a sacrificial layer from a first composite structure, wherein the first composite structure includes a first substrate structure; performing a heat treatment to release a gas from the first composite structure; performing a cleaning process to remove an oxide layer from the first composite structure; and combining the first composite structure with a second composite structure that includes a second substrate structure and an electronic component positioned on the second substrate substructure, such that the first substrate structure is combined with the second substrate structure to form an enclosure structure that encloses the electronic component.

Abstract: A package includes a package substrate, which includes a middle layer selected from the group consisting of a core and a middle metal layer, a top metal layer overlying the middle layer, and a bottom metal layer underlying the middle layer. All metal layers overlying the middle layer have a first total metal density that is equal to a sum of all densities of all metal layers over the middle layer. All metal layers underlying the middle layer have a second total metal density that is equal to a sum of all densities of all metal layers under the middle layer. An absolute value of a difference between the first total metal density and the second total metal density is lower than about 0.1.

Abstract: A packaged integrated circuit (IC) device includes a flexible substrate having contact pads, an IC die mounted on the substrate and electrically connected to the contact pads, and conductive threads sewn into the substrate. The conductive threads have proximal ends electrically connected to corresponding ones of the contact pads with conductive bumps. The conductive threads eliminate the need for a complicated multi-layer substrate structure for interconnect fan-out so the substrate may be formed of a variety of materials such as cloth or paper.

Abstract: In order to prevent a crack from developing in an interlayer insulating film formed under a bonding pad due to impact forces, the bonding pad is formed so that small diameter metal plugs and large diameter metal plugs are arranged between a first metal film and a second metal film as an uppermost layer. Holes are formed in the centers of the larger diameter metal plugs and recessed portions are formed in surface areas of the second metal film above the large diameter metal plugs.

Abstract: A system and method of manufacture of an integrated circuit packaging system includes: a photoimagable dielectric layer having a trace opening for exposing the carrier; a trace within the trace opening; an inner solder resist layer directly on the photoimagable dielectric layer and the trace, the inner solder resist layer having a bond pad opening for exposing the trace; an integrated circuit over the inner solder resist layer, the integrated circuit electrically connected to the trace through the bond pad opening; an encapsulation directly on the integrated circuit and the inner solder resist layer; and an external interconnect electrically coupled to the trace and the integrated circuit.

Abstract: A semiconductor device 100 includes a first insulating material 110 attached to a second main surface 106b of a semiconductor chip 106, and a second insulating material 112 attached to side surfaces of the semiconductor chip 106, the first insulating material 110 and an island 102. The semiconductor chip 106 is fixed to the island 102 via the first insulating material 110 and the second insulating material 112. The first insulating material 110 ensures a high dielectric strength between the semiconductor chip 106 and the island 102. Though the second insulating material 112 having a modulus of elasticity greater than that of the first insulating material 110, the semiconductor chip 106 is firmly attached to the island 102.

Abstract: Provided is a chip on film (COF) type semiconductor package. The COF type semiconductor device includes a flexible film, an electrode pattern formed on the flexible film, a semiconductor device disposed on the electrode pattern, a conductive pad disposed between the electrode pattern and the semiconductor device to electrically connect the semiconductor device with the electrode pattern, and a first protective layer which seals the conductive pad and the semiconductor device and is formed on a portion of the electrode pattern and the semiconductor device. The first protective layer includes a heat conductive material for dissipating heat generated from the semiconductor device.

Abstract: A semiconductor having an active layer; a gate insulating film in contact with the semiconductor; a gate electrode opposite to the active layer through the gate insulating film; a first nitride insulating film formed over the active layer; a photosensitive organic resin film formed on the first nitride insulating film; a second nitride insulating film formed on the photosensitive organic resin film; and a wiring provided on the second, nitride insulating film. A first opening portion is provided in the photosensitive organic resin film, an inner wall surface of the first opening portion is covered with the second nitride insulating film, a second opening portion is provided in a laminate including the gate insulating film, the first nitride insulating film, and the second nitride insulating film inside the first opening portion, and the semiconductor is connected with the wiring through the first opening portion and the second opening portion.

Abstract: A semiconductor device includes a substrate including a first region and a second region, first conductive patterns disposed on the first region and spaced apart from each other by a first distance, second conductive patterns disposed on the second region and spaced apart from each other by a second distance greater than the first distance, and an interlayer insulating layer disposed between the second conductive patterns and including at least one recess region having a width corresponding to the first distance.

Abstract: A semiconductor device comprises a circuit layer composed of a conductive material, and a semiconductor element mounted on the circuit layer, wherein an underlayer having a porosity in the range of 5 to 55% is formed on one surface of the circuit layer, a bonding layer composed of a sintered body of a bonding material including an organic substance and at least one of metal particles and metal oxide particles is formed on the underlayer, and the circuit layer and the semiconductor element are bonded together via the underlayer and the bonding layer.

Abstract: The present invention relates to a semiconductor device and a method for manufacturing the same. Disclosed is a semiconductor device including a substrate, a conductive line on the substrate, and a seed layer between the substrate and the conductive line, the seed layer including cobalt titanium nitride.

Abstract: A package on packaging structure comprising a first package and a second package provides for improved thermal conduction and mechanical strength by the introduction of a thermally conductive substrate attached to the second package. The first package has a first substrate and a first integrated circuit. The second package has a second substrate containing through vias that has a first coefficient of thermal expansion. The second package also has a second integrated circuit having a second coefficient of thermal expansion located on the second substrate. The second coefficient of thermal expansion deviates from the first coefficient of thermal expansion by less than about 10 or less than about 5 parts-per-million per degree Celsius. A first set of conductive elements couples the first substrate and the second substrate. A second set of conductive elements couples the second substrate and the second integrated circuit.

Abstract: Embodiments of the present invention relate to a fixture design for pre-attachment package on package component assembly. The fixture design includes a plurality of pockets arranged in a N×M array. The plurality of pockets is sized to receive bottom packages. The fixture design includes global fiducials that are used to locate positions of the pockets on the fixture, and sets of local fiducials, with each set being specific to one of the pockets and used to refine the position of the location of a corresponding pocket. Each of the pockets can include one or more ear cuts for easy component placement and component removal. The fixture design can include a vacuum port for coupling with a vacuum source for drawing a vacuum to hold the bottom packages down. The fixture design can also include a cover that is used with the fixture to keep the components from being disturbed.

Abstract: A method of manufacturing a semiconductor device is provided, including forming a gate electrode of a dummy transistor device on a semiconductor substrate, forming a high-k material layer over and adjacent to the gate electrode and forming a metal layer on the high-k material layer over and adjacent to the gate electrode to form a capacitor.