Patents Examined by Jasmine Clark
  • Printed electronics
    Patent number: 9504150
    Abstract: Printed electronic device comprising a substrate onto at least one surface of which has been applied a layer of an electrically conductive ink comprising functionalized graphene sheets and at least one binder. A method of preparing printed electronic devices is further disclosed.
    Type: Grant
    Filed: June 26, 2015
    Date of Patent: November 22, 2016
    Assignees: THE TRUSTEES OF PRINCETON UNIVERSITY, VORBECK MATERIALS CORPORATION
    Inventors: John M. Crain, John S. Lettow, Ilhan A. Aksay, Sibel Korkut, Katherine S. Chiang, Chuan-Hua Chen, Robert K. Prud'Homme
  • Semiconductor device
    Patent number: 9490194
    Abstract: The semiconductor device includes a semiconductor element, a main lead and a resin package. The semiconductor element includes an obverse surface and a reverse surface spaced apart from each other in a thickness direction. The main lead supports the semiconductor element via the reverse surface of the semiconductor element. The resin package covers the entirety of the semiconductor element. The resin package covers the main lead in such a manner that a part of the main lead is exposed from the resin package. The semiconductor element includes a part that does not overlap the main lead as viewed in the thickness direction.
    Type: Grant
    Filed: December 3, 2015
    Date of Patent: November 8, 2016
    Assignee: ROHM CO., LTD.
    Inventors: Kensuke Mikado, Makoto Shibuya, Yasufumi Matsuoka
  • Anisotropic conductive film including conductive adhesive layer and semiconductor device connected by the same
    Patent number: 9490228
    Abstract: An anisotropic conductive film includes a conductive adhesive layer including conductive particles and insulating particles, and an insulating adhesive layer not including conductive particles. In the anisotropic conductive film, the conductive particles and the insulating particles of the conductive adhesive layer have a total particle density of 7.0×105/d2 to 10.0×105/d2 (particles) per square millimeter (mm2) (where d is a diameter of the conductive particles in ?m).
    Type: Grant
    Filed: March 28, 2014
    Date of Patent: November 8, 2016
    Assignee: CHEIL INDUSTRIES, INC.
    Inventors: Kyoung Soo Park, Soon Young Kwon, Ji Yeon Kim, Young Woo Park, Jae Sun Han, Ja Young Hwang
  • Overlay marks and semiconductor process using the overlay marks
    Patent number: 9490217
    Abstract: An overlay mark for determining the alignment between two separately generated patterns formed along with two successive layers above a substrate is provided in the present invention, wherein both the substrate and the overlay mark include at least two pattern zones having periodic structures with different orientations, and the periodic structures of the overlay mark are orthogonally overlapped with the periodic structures of the substrate.
    Type: Grant
    Filed: April 15, 2015
    Date of Patent: November 8, 2016
    Assignee: UNITED MICROELECTRONICS CORP.
    Inventors: Chia-Ching Lin, En-Chiuan Liou, Chia-Hung Wang, Sho-Shen Lee
  • Semiconductor device and method for producing same
    Patent number: 9484304
    Abstract: In order to prevent the detachment of a film which is a constituent part of an interlayer-insulating film, and to prevent a decline in the device properties of a semiconductor device, a semiconductor device is provided with an interlayer-insulating film having, in this order, a carbon-containing silicon nitride (SiCN) film, a first silicon nitride film, and a silicon oxide film or a carbon-containing silicon oxide (SiOC) film.
    Type: Grant
    Filed: August 30, 2013
    Date of Patent: November 1, 2016
    Assignee: LONGITUDE SEMICONDUCTOR S.A.R.L.
    Inventors: Kazuhiro Okuda, Shigeo Ishikawa, Hiroshi Amaike
  • Power distribution improvement using pseudo-ESR control of an embedded passive capacitor
    Patent number: 9472425
    Abstract: A fan-out wafer level package structure may include a multilayer redistribution layer (RDL). The multilayer RDL may be configured to couple with terminals of an embedded capacitor. The multilayer RDL may include sections with fewer layers than other sections of the multilayer RDL according to a selected equivalent series resistance (ESR) control pattern.
    Type: Grant
    Filed: March 19, 2015
    Date of Patent: October 18, 2016
    Assignee: QUALCOMM INCORPORATED
    Inventors: Young Kyu Song, Kyu-Pyung Hwang, Jae Sik Lee
  • Semiconductor package and manufacturing method thereof
    Patent number: 9466580
    Abstract: A semiconductor device structure and a method for manufacturing a semiconductor device. As a non-limiting example, various aspects of this disclosure provide a semiconductor device structure (e.g., a sensor device structure), and method for manufacturing thereof, that comprises a three-dimensional package structure free of wire bonds, through silicon vias, and/or flip-chip bonding.
    Type: Grant
    Filed: July 31, 2015
    Date of Patent: October 11, 2016
    Inventors: Jong Sik Paek, No Sun Park
  • Distributed on-chip decoupling apparatus and method using package interconnect
    Patent number: 9466568
    Abstract: An integrated circuit device is disclosed. The integrated circuit device includes a semiconductor die fabricated by a front-end semiconductor process and having oppositely disposed planar surfaces. The semiconductor die is formed with semiconductor devices, power supply circuitry coupled to the semiconductor devices, decoupling capacitance circuitry, and through-vias. The through-vias include a first group of vias coupled to the power supply circuitry and a second group of vias coupled to the decoupling capacitance circuitry. Conductors are formed in a first metal layer disposed on the semiconductor die in accordance with a back-end semiconductor process. The conductors are configured to couple to the first and second groups of through-vias to establish conductive paths from the power supply circuitry to the decoupling capacitance circuitry.
    Type: Grant
    Filed: April 9, 2015
    Date of Patent: October 11, 2016
    Assignee: Rambus Inc.
    Inventors: David Secker, Ling Yang, Chanh Tran, Ying Ji
  • Semiconductor device and method for fabricating the same
    Patent number: 9466564
    Abstract: A semiconductor device is disclosed. The semiconductor device includes: a substrate having a gate structure thereon and a first interlayer dielectric (ILD) layer surrounding the gate structure; a first hard mask on the gate structure; and a second hard mask on the gate structure, wherein the first hard mask is adjacent to two sides of the second hard mask and the first hard mask and the first hard mask comprises silicon nitride.
    Type: Grant
    Filed: April 22, 2015
    Date of Patent: October 11, 2016
    Assignee: UNITED MICROELECTRONICS CORP.
    Inventors: En-Chiuan Liou, Chih-Wei Yang, Chih-Sen Huang, Yu-Cheng Tung
  • Electric connection element manufacturing method
    Patent number: 9460960
    Abstract: A surface of a silicon substrate is coated with a silicon oxide layer. A manganese silicate layer is then deposited on the silicon oxide layer using a process of performing at least one step of dipping the substrate into a manganese amidinate solution. A copper layer is then deposited on the manganese silicate layer using a process of performing a step of dipping the substrate into a copper amidinate solution. An anneal is performed to stabilize one or both of the manganese silicate layer and copper layer.
    Type: Grant
    Filed: August 28, 2015
    Date of Patent: October 4, 2016
    Assignees: STMICROELECTRONICS (TOURS) SAS, Centre National de la Recherche Scientifique-CNRS
    Inventors: Kilian Piettre, Pierre Fau, Jeremy Cure, Bruno Chaudret
  • Fan-out PoP structure with inconsecutive polymer layer
    Patent number: 9461018
    Abstract: A package includes a device die, a molding material molding at least a portion of the device die therein, and a through-via substantially penetrating through the molding material. The package further includes a dielectric layer contacting the through-via and the molding material, and a die attach film attached to a backside of the device die. The die attach film includes a portion extending in the dielectric layer.
    Type: Grant
    Filed: April 17, 2015
    Date of Patent: October 4, 2016
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Yi-Lin Tsai, Jeffrey Chang, Jing-Cheng Lin, Nai-Wei Liu, Tsei-Chung Fu
  • Electronic package that includes a plurality of integrated circuit devices bonded in a three-dimensional stack arrangement
    Patent number: 9461017
    Abstract: An electronic package comprising a plurality of vertically stacked integrated circuit (IC) devices including a first IC device and a second IC device is provided. The electronic package also includes a first bonding layer coupling one side of the first IC device entirely to a portion of a side of the second IC device. The remaining portion of the side of the second IC device that is not coupled to the one side of the first IC device, includes an antenna.
    Type: Grant
    Filed: April 13, 2015
    Date of Patent: October 4, 2016
    Assignee: GLOBALFOUNDRIES Inc.
    Inventors: Mukta G. Farooq, John A. Fitzsimmons, Andrew H. Simon, Anthony K. Stamper
  • Semiconductor package including an embedded surface mount device and method of forming the same
    Patent number: 9461020
    Abstract: Embodiments of the present disclosure include semiconductor packages and methods of forming the same. An embodiment is a semiconductor package including a first package including one or more dies, and a package substrate bonded to a first side of the first package with by a first set of connectors. The semiconductor package further includes a surface mount device mounted to the first side of the first package, the surface mount device consisting essentially of one or more passive devices.
    Type: Grant
    Filed: November 23, 2015
    Date of Patent: October 4, 2016
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Der-Chyang Yeh, Hsien-Wei Chen, Ming-Yen Chiu, Ying-Ju Chen
  • Semiconductor packages and methods of fabricating the same
    Patent number: 9455230
    Abstract: A semiconductor package includes a semiconductor chip electrically connected to a substrate, and a molding part including first molding members and second molding members arranged in an alternating pattern. The first molding members have a first physical flexibility which is different from a second physical flexibility of the second molding members.
    Type: Grant
    Filed: October 8, 2015
    Date of Patent: September 27, 2016
    Assignee: SK hynix Inc.
    Inventors: Yeon Ji Park, Hyeon Ji Baek, Ki Yong Lee, Jong Hyun Kim
  • Semiconductor structure and method for manufacturing the same
    Patent number: 9455403
    Abstract: A semiconductor structure and a method for manufacturing the same are provided. The semiconductor structure comprises an access device, a dielectric layer, a barrier layer, a first interlayer conductor, a first barrier liner, a second interlayer conductor, a second barrier liner, a memory element and a top electrode layer. The access device has two terminals. The dielectric layer covers the access device. The barrier layer is disposed on the dielectric layer. The first and second interlayer conductors are connected to the two terminals, respectively. The first and second barrier liners are disposed on sidewalls of the first and second interlayer conductors, respectively. The memory element is disposed on the first interlayer conductor. The top electrode layer is disposed on the barrier layer and the memory element and covers the memory element.
    Type: Grant
    Filed: August 28, 2015
    Date of Patent: September 27, 2016
    Assignee: MACRONIX INTERNATIONAL CO., LTD.
    Inventors: Erh-Kun Lai, Feng-Min Lee, Yu-Yu Lin, Dai-Ying Lee
  • Fan-out wafer level package and manufacturing method thereof
    Patent number: 9449911
    Abstract: Provided are a wafer level package and a manufacturing method thereof. The wafer level package method includes preparing a patterned wafer, forming a recess in a position, in which a semiconductor chip is to be attached, of the patterned wafer through an etching process, fixing the semiconductor chip to the interior of the recess, and applying a passivation material to portions other than the semiconductor chip within the recess and to an upper end of the wafer. The wafer level package includes a silicon or glass wafer including a recess formed through etching and having an area larger than a semiconductor chip, a semiconductor chip fixed to the interior of the recess, and a passivation material filling an empty space other than the semiconductor chip within the recess and applied to a portion corresponding to an area larger than the semiconductor chip on an upper end of the wafer.
    Type: Grant
    Filed: July 16, 2015
    Date of Patent: September 20, 2016
    Assignee: STS SEMICONDUCTOR & TELECOMMUNICATIONS CO., LTD.
    Inventors: Hee Cheol Kim, Jae Hyun Yoo, Young Seok Lee
  • Package-on-package assembly and method for manufacturing the same
    Patent number: 9449953
    Abstract: A package-on-package (PoP) assembly includes a bottom die package and a top die package mounted on the bottom die package. The bottom die package includes an interposer having a first side and a second side opposite to the first side, at least one chip mounted on the first side within a chip mounting area through a plurality of bumps, a molding compound disposed on the first side, the molding compound covering the at least one chip, and a plurality of peripheral bump structures penetrating through the molding compound within the peripheral area. Each of the peripheral bump structures includes conductive pillar and a partial TMV directly stacked on the conductive pillar. A plurality of solder balls is mounted on the second side of the interposer. The top die package is electrically connected to the peripheral bump structures.
    Type: Grant
    Filed: October 8, 2015
    Date of Patent: September 20, 2016
    Assignee: INOTERA MEMORIES, INC.
    Inventors: Shing-Yih Shih, Neng-Tai Shih
  • Chip support substrate, chip support method, three-dimensional integrated circuit, assembly device, and fabrication method of three-dimensional integrated circuit
    Patent number: 9449948
    Abstract: The present invention relates to a chip support substrate including a lyophilic region 4 that is formed on the substrate and that absorbs a chip 3A, and an electrode 6 that is formed on the substrate and in the lyophilic region and that generates electrostatic force in the chip, and to a chip support method including the steps of arranging the chip onto the lyophilic region of the chip support substrate with a liquid 15, the chip support substrate comprising the lyophilic region that is formed on the substrate, and the electrode that is formed on the substrate and in the lyophilic region, and generating the electrostatic force in the chip corresponding to the electrode by applying a voltage to the electrode.
    Type: Grant
    Filed: September 13, 2013
    Date of Patent: September 20, 2016
    Assignee: TOHOKU UNIVERSITY
    Inventors: Mitsumasa Koyanagi, Tetsu Tanaka, Takafumi Fukushima
  • Semiconductor device
    Patent number: 9443811
    Abstract: A semiconductor device comprises: a pad group including a plurality of pads provided on a semiconductor substrate and arranged in a row to form a pad row as a whole. The pad group includes: at least one first pad provided with a first via-connection part electrically connected therewith and extended in a first direction perpendicular to a row direction of the pad row; and at least one second pad provided with a second via-connection part electrically connected therewith and extended in a second direction opposite to the first direction. The at least one second pad is formed at a position moved in the first direction from the row direction of the pad row passing through a center of the at least one first pad.
    Type: Grant
    Filed: July 14, 2015
    Date of Patent: September 13, 2016
    Assignee: LAPIS SEMICONDUCTOR CO., LTD.
    Inventor: Nobutaka Nasu
  • Semiconductor device and manufacturing method thereof
    Patent number: 9443778
    Abstract: It is possible to provide a semiconductor device which can be obtained at a high reliability by warping an insulating substrate stably into a convex shape while ensuring a close contact between a cooling member and the insulating substrate. The semiconductor device includes an insulating substrate, a semiconductor element disposed on a first surface of the insulating substrate, a case connected to the insulating substrate, and a resin filled inside the case. Assuming that the thickness of the insulating substrate is denoted by t1, the thickness of the resin is denoted by t2, the linear expansion coefficient of the insulating substrate is denoted by ?1, and the linear expansion coefficient of the resin is denoted by ?2, the relationship therebetween satisfies t2?t1 and ?2??1, and a second surface of the insulating substrate opposite to the first surface thereof is warped into a convex shape.
    Type: Grant
    Filed: May 20, 2015
    Date of Patent: September 13, 2016
    Assignee: Mitsubishi Electric Corporation
    Inventors: Yoshitaka Otsubo, Hiroshi Yoshida, Junji Fujino, Masao Kikuchi, Junichi Murai