Abstract: A bonded device structure including a first substrate having a first set of conductive contact structures, preferably connected to a device or circuit, and having a first non-metallic region adjacent to the contact structures on the first substrate, a second substrate having a second set of conductive contact structures, preferably connected to a device or circuit, and having a second non-metallic region adjacent to the contact structures on the second substrate, and a contact-bonded interface between the first and second set of contact structures formed by contact bonding of the first non-metallic region to the second non-metallic region. The contact structures include elongated contact features, such as individual lines or lines connected in a grid, that are non-parallel on the two substrates, making contact at intersections. Alignment tolerances are thus improved while minimizing dishing and parasitic capacitance.

Abstract: Fan-out wafer-level packaging (WLP) using metal foil lamination is provided. An example wafer-level package incorporates a metal foil, such as copper (Cu), to relocate bonding pads in lieu of a conventional deposited or plated RDL. A polymer such as an epoxy layer adheres the metal foil to the package creating conductive contacts between the metal foil and metal pillars of a die. The metal foil may be patterned at different stages of a fabrication process. An example wafer-level package with metal foil provides relatively inexpensive electroplating-free traces that replace expensive RDL processes. Example techniques can reduce interfacial stress at fan-out areas to enhance package reliability, and enable smaller chips to be used. The metal foil provides improved fidelity of high frequency signals. The metal foil can be bonded to metallic pillar bumps before molding, resulting in less impact on the mold material.

Abstract: The present disclosure relates to semiconductor structures and, more particularly, to Through-Silicon Via (TSV) structures with improved substrate contact and methods of manufacture. The structure includes: a substrate of a first species type; a layer of different species type on the substrate; a through substrate via formed through the substrate and comprising an insulator sidewall and conductive fill material; a second species type adjacent the through substrate via; a first contact in electrical contact with the layer of different species type; and a second contact in electrical contact with the conductive fill material of the through substrate via.

Abstract: Disclosed herein is a semiconductor device that includes a semiconductor die and a substrate including a first surface and a second surface. The substrate includes a conductive circuit and an insulative material over the conductive circuit. The semiconductor die is attached to the second surface. The semiconductor device further includes an interconnect joint structure in the substrate creating a capture pad including a middle copper layer, an adjacent top nickel layer, and an adjacent bottom nickel layer. A method for making a semiconductor device is further disclosed.

Abstract: A package includes a first molding material, a lower-level device die in the first molding material, a dielectric layer over the lower-level device die and the first molding material, and a plurality of redistribution lines extending into the first dielectric layer to electrically couple to the lower-level device die. The package further includes an upper-level device die over the dielectric layer, and a second molding material molding the upper-level device die therein. A bottom surface of a portion of the second molding material contacts a top surface of the first molding material.

Abstract: Provided is a semiconductor device including: a first external electrode which includes a circular outer peripheral portion; a MOSFET chip; a control circuit chip which receives voltages of a drain electrode and a source electrode of the MOSFET and supplies a signal to a gate electrode to control the MOSFET on the basis of the voltage; a second external electrode which is disposed on an opposite side of the first external electrode with respect to the MOSFET chip and includes an external terminal on a center axis of the circular outer peripheral portion of the first external electrode; and an isolation substrate which isolates the control circuit chip from the external electrode. The first external electrode, the drain electrode and the source electrode of the MOSFET chip, and the second external electrode are disposed to be overlapped in a direction of the center axis. The drain electrode of the MOSFET chip and the first external electrode are connected.

Abstract: A three-dimensional semiconductor device includes a plurality of stack structures extending in one direction on a substrate and spaced apart from each other, a plurality of vertical structures penetrating the stack structures, a common source plug between the stack structures that are adjacent to each other and extending in parallel to the stack structures, and a spacer structure at each side of the common source plug. The stack structure has a sidewall defining recess regions vertically spaced apart from each other. The spacer structure covers sidewalls of the stack structures. The spacer structure includes an insulating spacer and a protection spacer. The insulating spacer fills the recess regions of the stack structure and includes a surface having grooves. The protection spacer fills the grooves of the surface of the insulating spacer and has a substantially flat surface.

Abstract: According to various embodiments, a chip carrier may include: a chip supporting region configured to support a chip; a chip contacting region including at least one contact pad for electrically contacting the chip; wherein the chip carrier is thinned in the chip contacting region such that a first thickness of the chip carrier at the at least one contact pad is smaller than a second thickness of the chip carrier in the chip supporting region.

Abstract: Molded electronics package cavities are formed by placing a sacrificial material in the mold and then decomposing, washing, or etching away this sacrificial material. The electronics package that includes this sacrificial material is then overmolded, with little or no change needed in the overmolding process. Following overmolding, the sacrificial material is removed such as using a thermal, chemical, optical, or other decomposing process. This proposed use of sacrificial material allows for formation of complex 3-D cavities, and reduces or eliminates the need for precise material removal tolerances. Multiple instances of the sacrificial material may be removed simultaneously, replacing a serial drilling process with a parallel material removal manufacturing process.

Abstract: A wiring board includes: a core substrate including: a metal plate having first through holes; a first insulating layer covering an upper surface and a lower surface of the metal plate and inner wall surfaces of the first through holes; through electrodes penetrating the first insulating layer in a thickness direction and each having an upper end surface; a first wiring layer formed on a lower surface of the first insulating layer and connected to the through electrodes; a wiring structure formed on an upper surface of the first insulating layer; and an outermost insulating layer formed on a lower surface of the core substrate. A wiring density of the wiring structure is higher than that of the core substrate. The metal plate is located at a side of the wiring structure with respect to a center of the first insulating layer in a thickness direction thereof.

Abstract: An electronic device includes a carrier substrate with at least one electronic-circuit chip mounted on a front face of the carrier substrate. An encapsulation block on the front face and embedding the electronic-circuit chip has a periphery with corners. The encapsulating block further has, in at least one local zone located in at least one corner and from the front face of the carrier substrate, a smaller thickness than a thickness of the encapsulation block at least in a surrounding zone. The electronic device is manufactured by a process in which the zone of smaller thickness is obtained by molding or by machining.

Abstract: A method of packaging a semiconductor die includes the steps of mounting the semiconductor die on a carrier, electrically connecting electrical contact pads of the semiconductor die to external electrical contacts, and encapsulating the die with a mold compound to form a packaged die. The packaged die is then thinned by using a dicing saw blade to trim the mold compound off of the top, non-active side of the package using a series of vertical cuts. This thinning step can be performed at the same time as a normal dicing step so no additional equipment or process steps are needed. Further, packages of varying thicknesses can be assembled simultaneously.

Abstract: Disclosed herein is a semiconductor device that includes a semiconductor die and a substrate including a first surface and a second surface. The substrate includes a conductive circuit and an insulative material over the conductive circuit. The semiconductor die is attached to the second surface. The semiconductor device further includes an interconnect joint structure in the substrate creating a capture pad including a middle copper layer, an adjacent top nickel layer, and an adjacent bottom nickel layer. A method for making a semiconductor device is further disclosed.

Abstract: An integrated circuit (IC) device may include a first substrate having an inductor ground plane in a conductive layer of the first substrate. The integrated circuit may also include a first inductor in a passive device layer of a second substrate that is supported by the first substrate. A shape of the inductor ground plane may substantially correspond to a silhouette of the first inductor.

Abstract: A semiconductor wafer including a main body including first and second surfaces opposite each other, a notch including a recess on an outer periphery, a first bevel region formed along the outer periphery of the main body, including a first slope connecting the first and second surfaces and having a first height with respect to a straight line extending from a first point where the first surface and the first slope meet to a second point where the second surface and the first slope meet, and a second bevel region in contact with the recess or opening, including a second slope connecting the first and second surfaces and having a second height, different from the first height, with respect to a straight line extending from a third point where the first surface and the second slope meet to a fourth point where the second surface and the second slope meet.

Abstract: An epoxy resin composition, comprising an epoxy resin, a curing agent, a curing accelerator, an inorganic filler, and a carboxylic acid compound that satisfies at least one selected from the group consisting of the following A, B and C below: A: having at least one carboxy group and at least one hydroxy group; B: having at least two carboxy groups; and C: having a structure in which two carboxy groups are condensed by dehydration.

Abstract: The present disclosure provides a method of forming a biocompatible structure that includes forming biodissolvable substrate comprising a flexible network of peptides, and a biocompatible structure having a biodissolvable substrate and, optionally, an electronic device on a surface thereof for use in implantable electronics.

Abstract: Aspects of the disclosure are directed to integrated circuit dies and their manufacture. In accordance with one or more embodiments, a plurality of integrated circuit dies are provided in a semiconductor wafer, with each integrated circuit die having: an integrated circuit within the die, a via extending from a first surface to a second surface that opposes the first surface, and first and second electrical contacts at the first surface respectively coupled to the via and to the integrated circuit. Lanes are created in a front side of the wafer between the dies, and a portion of the back side of the wafer is removed to expose the lanes. A further contact and/or via is also exposed at the backside, with the via providing an electrical signal path for coupling electrical signals through the integrated circuit die (e.g., bypassing circuitry therein).

Abstract: A semiconductor device is disclosed. The semiconductor device has a semiconductor chip, an island having an upper surface to which the semiconductor chip is bonded, a lead disposed around the island, a bonding wire extended between the surface of the semiconductor chip and the upper surface of the lead, and a resin package sealing the semiconductor chip, the island, the lead, and the bonding wire, while the lower surface of the island and the lower surface of the lead are exposed on the rear surface of the resin package, and the lead is provided with a recess concaved from the lower surface side and opened on a side surface thereof.

Abstract: A three-dimensional structure in which a wiring is provided on a surface is provided. At least a part of the surface of the three-dimensional structure includes an insulating layer containing filler. A recessed gutter for wiring is provided on the surface of the three-dimensional structure, and at least a part of a wiring conductor is embedded in the recessed gutter for wiring.