Patents Examined by Jasmine Clark
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Patent number: 9640455Abstract: A semiconductor device has a semiconductor element provided with a functional surface on which a functional circuit is formed and with a back surface facing in the opposite direction to the functional surface, while also having a lead supporting the semiconductor element and electrically connected to the semiconductor element, and a resin package covering at least a portion of the semiconductor element and the lead. The semiconductor element has a functional surface side electrode formed on the functional surface and equipped with a functional surface side raised part that projects in the direction in which the functional surface faces. The functional surface side raised part of the functional surface side electrode is joined to the lead by solid state bonding.Type: GrantFiled: April 12, 2016Date of Patent: May 2, 2017Assignee: ROHM CO., LTD.Inventors: Kenji Fujii, Yasumasa Kasuya, Mamoru Yamagami, Naoki Kinoshita, Motoharu Haga
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Patent number: 9633966Abstract: A stacked semiconductor package and a manufacturing method thereof. For example and without limitation, various aspects of this disclosure provide a semiconductor package in which an upper interposer and/or package are electrically and mechanically coupled to a lower package utilizing an adhesive member comprising conductive particles.Type: GrantFiled: October 7, 2015Date of Patent: April 25, 2017Assignee: AMKOR TECHNOLOGY, INC.Inventors: Dong Joo Park, Jae Sung Park, Jin Seong Kim, Ju Hoon Yoon
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Patent number: 9631065Abstract: Methods of forming microelectronic packaging structures and associated structures formed thereby are described. Those methods and structures may include forming a wafer level underfill (WLUF) material comprising a resin material, and adding at least one of a UV absorber, a sterically hindered amine light stabilizer (HALS), an organic surface protectant (OSP), and a fluxing agent to form the WLUF material. The WLUF is then applied to a top surface of a wafer comprising a plurality of die.Type: GrantFiled: March 12, 2013Date of Patent: April 25, 2017Assignee: Intel CorporationInventors: Anna M. Prakash, James C. Matayabas, Arjun Krishnan, Nisha Ananthakrishnan
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Patent number: 9633981Abstract: A method of ultrasonically bonding semiconductor elements includes the steps of: (a) aligning surfaces of a plurality of first conductive structures of a first semiconductor element to respective surfaces of a plurality of second conductive structures of a second semiconductor element, wherein the surfaces of each of the plurality of first conductive structures and the plurality of second conductive structures include aluminum; and (b) ultrasonically bonding ones of the first conductive structures to respective ones of the second conductive structures.Type: GrantFiled: May 5, 2016Date of Patent: April 25, 2017Assignee: Kulicke and Soffa Industries, Inc.Inventors: Robert N. Chylak, Dominick A. DeAngelis
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Patent number: 9633975Abstract: A microelectronic package can include a substrate having first and second opposed surfaces extending in first and second transverse directions and an opening extending between the first and second surfaces and defining first and second distinct parts each elongated along a common axis extending in the first direction, first and second microelectronic elements each having a front surface facing the first surface of the substrate and a column of contacts at the respective front surface, a plurality of terminals exposed at the second surface, and first and second electrical connections aligned with the respective first and second parts of the opening and extending from at least some of the contacts of the respective first and second microelectronic elements to at least some of the terminals. The column of contacts of the first and second microelectronic elements can be aligned with the respective first and second parts of the opening.Type: GrantFiled: April 18, 2016Date of Patent: April 25, 2017Assignee: Invensas CorporationInventors: Belgacem Haba, Wael Zohni
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Patent number: 9633925Abstract: Structures and methods for improving the visualization of alignment marks on an underfill-covered chip. A feature is formed on a chip, and an underfill material is applied to the chip at a wafer level so that the feature is covered the feature. The feature includes a first structural element comprised of a first material and a second structural element comprised of a second material that is electrochemically dissimilar from the first material to provide a galvanic cell effect. Filler particles in the underfill material are caused by the galvanic cell effect to distribute with a first density in a first region over the first structural element and a second region of a second density over the second structural element. The first density in the first region is less than the second density in the second region such that the first region has a lower opacity than the second region.Type: GrantFiled: March 25, 2016Date of Patent: April 25, 2017Assignee: GLOBALFOUNDRIES Inc.Inventors: Katsuyuki Sakuma, Mukta G. Farooq, Jae-Woong Nah
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Patent number: 9627298Abstract: To enable a semiconductor device excellent in usability to be provided. A semiconductor device has a main surface surrounded by a plurality of sides, a semiconductor chip having a plurality of electrode pads arranged over the main surface, and a plurality of leads coupled to the electrode pads by way of wires respectively. The electrode pads include a plurality of first electrode pads supplied with a plurality of bits temporally in parallel. The first electrode pads include second and third electrode pads. A fourth electrode pad different from the first electrode pads is arranged between the second and third electrode pads.Type: GrantFiled: November 12, 2015Date of Patent: April 18, 2017Assignee: RENESAS ELECTRONICS CORPORATIONInventor: Teruaki Kanzaki
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Patent number: 9624369Abstract: A liquid resin composition includes a liquid epoxy resin, a liquid curing agent, a curing accelerator and a ceramic filler. The liquid epoxy resin contains a first epoxy resin having a polyalkylene glycol framework. The liquid curing agent has a plurality of phenolic hydroxy groups per molecule. A content of the first epoxy resin in the liquid epoxy resin is in a range from 30% to 70% by mass, inclusive. The ceramic filler has an average particle diameter of 50 ?m or less, and a content of the ceramic filler in the liquid resin composition is in a range from 50% to 90% by mass, inclusive. The liquid resin composition has a viscosity of 100 Pa·s or less at 25° C.Type: GrantFiled: March 24, 2015Date of Patent: April 18, 2017Assignee: Panasonic Intellectual Property Management Co., Ltd.Inventors: Takashi Hasegawa, Takanori Konishi
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Patent number: 9617455Abstract: A silicone resin composition is provided that exhibits an increased adhesiveness relative to insulating circuit substrates and can prevent bubble production even when moisture absorption has occurred, exhibits an excellent heat resistance, and is free of problems such as cracking. A silicone resin composition for use as a sealant for a power semiconductor module includes an insulating circuit substrate having a Cu layer formed on a surface thereof. The silicone resin composition is formed on the Cu layer of the insulating circuit substrate, and has, after curing, a penetration of 35 to 70 and an adhesive strength of 50 to 180 kPa between the silicone resin composition and the insulating circuit substrate. The penetration is measured in accordance with JIS K 2220.Type: GrantFiled: April 5, 2016Date of Patent: April 11, 2017Assignee: FUJI ELECTRIC CO., LTD.Inventors: Makoto Higashidate, Yuji Ichimura
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Patent number: 9620427Abstract: A semiconductor device may include an enclosure structure. The semiconductor device may further include a getter for absorb gas molecules. The getter may be positioned (and enclosed) inside the enclosure structure and may overlap a first portion of a surface of the enclosure structure. The semiconductor device may further include an inductor. The inductor may be positioned (and enclosed) inside the enclosure structure and may overlap a second portion of the surface of the enclosure structure without overlapping the getter in a direction perpendicular to the first surface of the enclosure structure.Type: GrantFiled: April 14, 2016Date of Patent: April 11, 2017Assignee: SEMICONDUCTOR MANUFACTURING INTERNATIONAL (SHANGHAI) CORPORATIONInventors: Chao Zheng, Junde Ma, Liangliang Guo, Wei Wang
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Patent number: 9607939Abstract: A semiconductor package is provided, including a semiconductor substrate having a plurality of conductive vias, a buffer layer formed on the semiconductor substrate, a plurality of conductive pads formed on end surfaces of the conductive vias and covering the buffer layer. During a reflow process, the buffer layer greatly reduces the thermal stress, thereby eliminating the occurance of cracking at the interface of conductive pads. A method of fabricating such a semiconductor package is also provided.Type: GrantFiled: April 23, 2014Date of Patent: March 28, 2017Assignee: Siliconware Precision Industries Co., Ltd.Inventors: Wen-Tsung Tseng, Yi-Che Lai, Shih-Kuang Chiu, Mao-Hua Yeh
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Patent number: 9607941Abstract: A method for fabricating a conductive via structure is provided, which includes the steps of: forming in an encapsulant a plurality of openings penetrating therethrough; forming a dielectric layer on the encapsulant and in the openings of the encapsulant; forming a plurality of vias in the dielectric layer in the openings of the encapsulant; and forming a conductive material in the vias to thereby form conductive vias. Therefore, by filling the openings having rough wall surfaces with the dielectric layer so as to form the vias having even wall surfaces, the present invention improves the quality of the conductive vias.Type: GrantFiled: March 26, 2015Date of Patent: March 28, 2017Assignee: Siliconware Precision Industries Co., Ltd.Inventors: Yan-Heng Chen, Chun-Tang Lin, Chieh-Yuan Chi, Mu-Hsuan Chan
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Patent number: 9607932Abstract: A semiconductor device is disclosed. The semiconductor device has a semiconductor chip, an island having an upper surface to which the semiconductor chip is bonded, a lead disposed around the island, a bonding wire extended between the surface of the semiconductor chip and the upper surface of the lead, and a resin package sealing the semiconductor chip, the island, the lead, and the bonding wire, while the lower surface of the island and the lower surface of the lead are exposed on the rear surface of the resin package, and the lead is provided with a recess concaved from the lower surface side and opened on a side surface thereof.Type: GrantFiled: April 8, 2016Date of Patent: March 28, 2017Assignee: ROHM CO., LTD.Inventors: Akihiro Koga, Taro Nishioka
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Patent number: 9607892Abstract: A method for fabricating semiconductor device comprising: providing a substrate having a gate structure thereon and a first interlayer dielectric (ILD) layer surrounding the gate structure; removing part of the gate structure; forming a first mask layer on the first ILD layer and the gate structure; removing the first mask layer on the first ILD layer and part of the first mask layer on the gate structure for forming a first hard mask on the gate structure; forming a second mask layer on the first ILD layer, the first hard mask, and the gate structure; and planarizing the second mask layer to form a second hard mask on the gate structure, in which the top surfaces of the first hard mask, the second hard mask, and the first ILD layer are coplanar.Type: GrantFiled: July 4, 2016Date of Patent: March 28, 2017Assignee: UNITED MICROELECTRONICS CORP.Inventors: En-Chiuan Liou, Chih-Wei Yang, Chih-Sen Huang, Yu-Cheng Tung
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Patent number: 9601424Abstract: A method of forming and testing an interposer includes forming vias in a semiconductor material of a wafer having a front side and a back side. The method further includes disposing an electrically conductive layer on the front side of the wafer such that the layer is electrically connected to the vias. The method also includes forming electrically conductive pads on the front side of the wafer, wherein each electrically conductive pad is electrically connected to the electrically conductive layer. The method further includes forming electrically conductive bumps on the back side of the wafer, wherein each electrically conductive bump is electrically connected to at least one via. The method also includes testing electrical connectivity from a first bump to a second bump of the electrically conductive bumps.Type: GrantFiled: April 13, 2015Date of Patent: March 21, 2017Assignee: GLOBALFOUNDRIES, INC.Inventors: Rahul Agarwal, Jens Oswald, Sheng Feng Lu, Soon Leng Tan, Jeffrey Lam
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Patent number: 9595492Abstract: Some embodiments of the present disclosure provide a semiconductive device. The semiconductive device includes a first conductive layer and a second conductive layer above the first conductive layer. The second conductive layer includes a first portion and a second portion protruding from the first portion. A via structure is under the second conductive layer and on top of the first conductive layer. The via structure is substantially aligned vertically with the second portion.Type: GrantFiled: March 16, 2015Date of Patent: March 14, 2017Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY LTD.Inventor: Chien-Hsuan Liu
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Patent number: 9595482Abstract: A package includes a device die, which includes a metal pillar at a top surface of the device die, and a solder region on a sidewall of the metal pillar. A molding material encircles the device die, wherein a top surface of the molding material is substantially level with a top surface of the device die. A dielectric layer overlaps the molding material and the device die, with a bottom surface of the dielectric layer contacting a top surface of the device die and a top surface of the molding material. A redistribution line (RDL) extends into the dielectric layer to electrically couple to the metal pillar.Type: GrantFiled: March 16, 2015Date of Patent: March 14, 2017Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.Inventor: Hsien-Wei Chen
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Patent number: 9589911Abstract: Embodiments of the present disclosure provide an integrated circuit (IC) structure with a metal crack stop and methods of forming the same. An IC structure according to embodiments of the present disclosure can include an insulator positioned over a substrate; a barrier film positioned over the insulator; an interlayer dielectric positioned over the barrier film; and a metal crack stop positioned over the substrate and laterally adjacent to each of the insulator, the barrier film, and the interlayer dielectric, wherein the metal crack stop includes a sidewall having a first recess therein, and wherein a horizontal interface between the barrier film and the interlayer dielectric intersects the sidewall of the metal crack stop.Type: GrantFiled: August 27, 2015Date of Patent: March 7, 2017Assignee: GLOBALFOUNDRIES INC.Inventors: Jim S. Liang, Atsushi Ogino, Roger A. Quon, Stephen E. Greco
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Patent number: 9589921Abstract: In one semiconductor device, a semiconductor chip has first and second pad electrodes disposed on the main surface thereof, insulating films that cover the main surface of the semiconductor chip, a rewiring layer that is disposed between the insulating films, and a plurality of external terminals disposed on the top of the insulating film. The plane size of the first pad electrode and the second pad electrode differ from one another, and the first pad electrode and the second pad electrode are connected to any of the plurality of external terminals via the rewiring layer.Type: GrantFiled: March 10, 2014Date of Patent: March 7, 2017Assignee: PS4 LUXCO S.A.R.L.Inventors: Mitsuaki Katagiri, Yu Hasegawa, Satoshi Isa
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Patent number: 9589938Abstract: Embodiments of the present disclosure include devices and methods of forming the same. An embodiment is a device including a solder resist coating over a first side of a substrate, an active surface of a die bonded to the first side of the substrate by a first connector, and a surface mount device mounted to the die by a second set of connectors, the surface mount device being between the die and the first side of the substrate, the surface mount device being spaced from the solder resist coating.Type: GrantFiled: December 28, 2015Date of Patent: March 7, 2017Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Hsien-Wei Chen, Ying-Ju Chen