Abstract: Die packages and method of manufacturing the same are disclosed. In an embodiment, a method of manufacturing a die package may include forming an encapsulated via structure including at least one via, a polymer layer encapsulating the at least one via, and a first molding compound encapsulating the polymer layer; placing the encapsulated via structure and a first die stack over a carrier, the at least one via having a first end proximal the carrier and a second end distal the carrier; encapsulating the first die stack and the encapsulated via structure in a second molding compound; and forming a first redistribution layer (RDL) over the second molding compound, the first RDL electrically connecting the at least one via.

Abstract: A copolymer according to the present disclosure is provided, which includes 30 to 80 mol % of a repeating unit represented by formula (I), 5 to 25 mol % of a repeating unit represented by formula (II), and 5 to 30 mol % of a repeating unit represented by formula (III): wherein R1 is C6-C13 aryl group, C7-C13 aralkyl group, C6-C8 halogenated aryl group or C7-C8 aryloxyalkyl group; R3 is C3-C16 alkyl group or C3-C6 alkoxy substituted alkyl group; R5 is a single bond or C1-C3 alkylene group, R6 and R7 are independently C1-C3 alkoxy group, R8 is polysiloxane with methyl and phenyl groups; and R2, R4 and R9 are independently hydrogen or methyl. In addition, a resin composition, a packaging film and a package structure including the same are provided.

Abstract: The present invention provides a nanoparticle of an inorganic oxide particle being surface-treated, wherein: a primary particle size of the nanoparticle measured by a dynamic light scattering method is 8 nm or more and 30 nm or less, and the inorganic oxide particle is surface-treated in such a way that alkoxy groups having 1 to 10 carbon atoms are contained in a range of 0.001 to 0.5 mol/100 g. The inventive nanoparticle, being added to a silicone resin composition, enables the cured product thereof to possess excellent mechanical properties, transparency, crack resistance, heat resistance, and gas barrier properties, and enables the composition to have low viscosity and good workability even after the addition of the nanoparticle.

Abstract: A wiring board includes: an insulating layer; and a wiring layer including: an upper surface; a lower surface opposite to the upper surface; and a side surface between the upper surface and the lower surface, wherein the upper surface of the wiring layer is exposed from the insulating layer, and the side surface and the lower surface of the wiring layer are embedded in the insulating layer. A recess portion is formed in an outer edge portion of the upper surface of the wiring layer, and the recess portion is filled with the insulating layer.

Abstract: A method for treating a chip packaging structure includes providing a chip packaging structure having at least a first electrical connect structure and a second electrical connect structure, and an insulation layer exposing portions of the first electrical connect structure and the second electrical connect structure; selecting a plasma gas based on materials of the first electrical connect structure and the second electrical connect structure and a type of process forming the first electrical connect structure and the second electrical connect structure, wherein metal cations are left on the insulation layer; performing a plasma treatment process using the selected plasma gas on the first electrical connect structure, the second electrical connect structure and the insulation layer, causing reaction of the metal cations to substantially convert the metal cations into electrically neutral materials; and removing the reacted metal cations from the insulation layer.

Abstract: An array substrate and a fabricating method thereof and a display apparatus are provided. The array substrate comprises a base substrate, a pixel electrode layer formed on the base substrate, and a first wire grid polarizing film disposed on a surface of the pixel electrode layer, wherein the first wire grid polarizing film includes a plurality of first metal lines (L1) which are mutually parallel and are periodically arranged; the surface of the pixel electrode layer is a surface of the pixel electrode layer facing the base substrate or a surface of the pixel electrode layer opposite to the base substrate. The array substrate and the fabricating method thereof and the display apparatus can facilitate an ultrathin design.

Abstract: A system and method of manufacture of an integrated circuit packaging system includes: a photoimagable dielectric layer having a trace opening for exposing the carrier; a trace within the trace opening; an inner solder resist layer directly on the photoimagable dielectric layer and the trace, the inner solder resist layer having a bond pad opening for exposing the trace; an integrated circuit over the inner solder resist layer, the integrated circuit electrically connected to the trace through the bond pad opening; an encapsulation directly on the integrated circuit and the inner solder resist layer; and an external interconnect electrically coupled to the trace and the integrated circuit.

Abstract: A package includes a first molding material, a lower-level device die in the first molding material, a dielectric layer over the lower-level device die and the first molding material, and a plurality of redistribution lines extending into the first dielectric layer to electrically couple to the lower-level device die. The package further includes an upper-level device die over the dielectric layer, and a second molding material molding the upper-level device die therein. A bottom surface of a portion of the second molding material contacts a top surface of the first molding material.

Abstract: An apparatus including a circuit substrate; a first interconnect layer in a first plane on the substrate and a second interconnect layer in a different second plane on the substrate; and a hardmask layer separating the first interconnect layer and the second interconnect layer, wherein the hardmask layer comprises alternating guide sections comprising different hard mask materials, and a via guide. A method including forming a dielectric layer on an integrated circuit structure; forming a first interconnect layer having interconnect lines in the dielectric layer; forming a hardmask layer on a surface of the dielectric layer, the hardmask layer comprising alternating hardmask materials which form guide sections over the interconnect lines; forming a via guide in one of the guide sections; and forming a second interconnect layer over the hardmask guide layer which is electrically connected to one of the interconnect lines through the via guide.

Abstract: The present invention provides a thermally curable resin sheet for sealing a semiconductor chip having excellent reliability and storability while being reduced in warpage deformation due to the volume shrinkage of the thermally curable resin sheet, and a method for manufacturing a semiconductor package. The present invention relates to a thermally curable resin sheet for sealing a semiconductor chip, wherein an activation energy (Ea) satisfies the following formula (1), a glass transition temperature of a product thermally cured at 150° C. for 1 hour is 125° C. or higher, and a thermal expansion coefficient ? [ppm/K] of the thermally cured product at the glass transition temperature or lower and a storage modulus E? [GPa] at 25° C. of the thermally cured product satisfy the following formula (2): 30?Ea?120 [kJ/mol]??(1); and 10,000??×E??300,000 [Pa/K]??(2).

Abstract: A method of manufacturing a semiconductor device includes: arranging a solder material containing at least tin, between a semiconductor element and a joined member provided with a nickel layer and a copper layer, such that the solder material is in contact with the copper layer, the nickel layer being provided on a surface of the joined member, and the copper layer being provided on at least a portion of a surface of the nickel layer; and melting and solidifying the solder material to form Cu6Sn5 on the surface of the nickel layer using tin of the solder material and the copper layer.

Abstract: A semiconductor apparatus has a configuration in which multiple copper wiring layers and multiple insulating layers are alternately layered. A low-impedance wiring is formed occupying a predetermined region. A first wiring pattern includes multiple copper wiring members arranged in parallel with predetermined intervals in a first copper wiring layer, each of which has a rectangular shape extending in a first direction. A second wiring pattern includes multiple copper wiring members arranged in parallel with predetermined intervals in a second copper wiring layer adjacent to the first copper wiring layer, each of which has a rectangular shape extending in a second direction orthogonal to the first direction. The region occupied by the first wiring pattern and that occupied by the second wiring pattern are arranged such that they at least overlap. The first wiring pattern and the second wiring pattern are electrically connected so as to have the same electric potential.

Abstract: A semiconductor device includes a pad group including pads provided on a semiconductor substrate and arranged in a row to form a pad row as a whole. The pad group includes at least one first pad provided with a first via-connection part electrically connected therewith and extending in a first direction perpendicular to a row direction of the pad row, and at least one second pad provided with a second via-connection part electrically connected therewith and extending in a second direction opposite to the first direction. The at least one second pad is formed at a position moved in the first direction from the row direction of the pad row passing through a center of the at least one first pad.

Abstract: A method for forming a chip package is provided. The method includes providing a first substrate and a second substrate. The first substrate is attached onto the second substrate by an adhesive layer. A first opening is formed to penetrate the first substrate and the adhesive layer and separate the first substrate and the adhesive layer into portions. A chip package formed by the method is also provided.

Abstract: In order, for example, to improve the ohmic contact between two metal pieces located at a metallization level, these two metal pieces are equipped with two offset vias located at the metallization level and at least partially at the via level immediately above. Each offset via comprises, for example, a nonoxidizable or substantially nonoxidizable compound, such as a barrier layer of Ti/TiN.

Abstract: A semiconductor package structure and a method for making a semiconductor package. As non-limiting examples, various aspects of this disclosure provide various semiconductor package structures, and methods for making thereof, that comprise a connect die that routes electrical signals between a plurality of other semiconductor die.

Abstract: Various methods and devices that involve phase change material (PCM) switches are disclosed. An exemplary integrated circuit comprises an active layer with a plurality of field effect transistor (FET) channels for a plurality of FETs. The integrated circuit also comprises an interconnect layer comprising a plurality of conductive interconnects. The plurality of conductive interconnects couple the plurality of field effect transistors. The integrated circuit also comprises an insulator layer covering at least a portion of the interconnect layer. The integrated circuit also comprises a channel of a radio-frequency (RF) PCM switch. The channel of the RF PCM switch is formed on the insulator layer.

Abstract: Fan-out wafer-level packaging (WLP) using metal foil lamination is provided. An example wafer-level package incorporates a metal foil, such as copper (Cu), to relocate bonding pads in lieu of a conventional deposited or plated RDL. A polymer such as an epoxy layer adheres the metal foil to the package creating conductive contacts between the metal foil and metal pillars of a die. The metal foil may be patterned at different stages of a fabrication process. An example wafer-level package with metal foil provides relatively inexpensive electroplating-free traces that replace expensive RDL processes. Example techniques can reduce interfacial stress at fan-out areas to enhance package reliability, and enable smaller chips to be used. The metal foil provides improved fidelity of high frequency signals. The metal foil can be bonded to metallic pillar bumps before molding, resulting in less impact on the mold material.

Abstract: A method of removing at least a portion of a layer of material from over a semiconductor substrate that can include dispensing an etching solution over the semiconductor substrate to form a pool of etching solution on the layer of material, wherein a footprint of the pool of etching solution is less than a footprint of the semiconductor substrate. The pool of etching solution and the semiconductor substrate can be moved with respect to each other. A pool boundary of the pool of etching solution can be defined on the semiconductor substrate with at least one air-knife such that the pool of etching solution etches the layer of material over the semiconductor substrate within the footprint of the pool of etching solution. The etching solution and at least a portion of the layer of material etched by the etching solution can be removed with the at least one air-knife.

Abstract: A package substrate and a semiconductor package are provided. The package substrate includes an insulating layer having opposing first and second surfaces; a first wiring layer formed in the insulating layer, exposed from the first surface of the insulating layer, and having a plurality of first conductive pads; a second wiring layer formed in the insulating layer, exposed from the second surface, and having a plurality of second conductive pads; a third wiring layer formed on the first surface and electrically connected with the first wiring layer; a plurality of first metal bumps formed on the first conductive pads corresponding; and at least one conductive via vertically embedded in the insulating layer and electrically connected to the second and third wiring layers. Therefore, the surfaces of first conductive pads are reduced, and the non-wetting between the first conductive pads and the solder materials formed on conductive bumps is avoided.