Abstract: A component mounting system and a method for inspecting mounted components are provided. A component mounting system according to an embodiment, comprises a solder inspection apparatus comparing coordinate information of the solder, which is obtained through measurement of a substrate to which solder is applied, with reference coordinate information to generate coordinate correction data; and a first mounting inspection apparatus comparing a first measurement data obtained by measuring mounting state of a component when the component is mounted based on the coordination correction data through a component mounting apparatus, with the coordinate correction data to verify whether a component is mounted on a position corrected based on the coordinate correction data. In this manner, by adding the verification function for the performance function of the component mounting apparatus to the inspection apparatus, it is possible to monitor the operation state of the component mounting apparatus in each process step.

Abstract: The present invention provides a semiconductor package structure including a first stacked structure and a second stacked structure, which is stacked on the first stacked structure. The first stacked structure includes a first dielectric layer, a first power chip, a first conductive connecting element, a first conductive pillar and a first patterned conductive layer. The second stacked structure includes a second dielectric layer, a second power chip, a second conductive connecting element, a second conductive pillar, a second patterned conductive layer, and a third patterned conductive layer. The first power chip and the second power chip are stacked to provide a smaller volume semiconductor package structure, that the first power chip and the second power chip may be directly electrically connected through the circuit structure and may eliminate the related disadvantages of the lead frame. In addition, a manufacturing method of a semiconductor package structure is also disclosed.

Abstract: A bonded structure can include a first element having a first conductive interface feature and a second element having a second conductive interface feature. An integrated device can be coupled to or formed with the first element or the second element. The first conductive interface feature can be directly bonded to the second conductive interface feature to define an interface structure. The interface structure can be disposed about the integrated device in an at least partially annular profile to connect the first and second elements.

Abstract: A chip-middle type fan-out panel-level package (FOPLP) has a routing layer, a polyimide layer formed on the routing layer and having a plurality of pillar openings and a chip opening, a plurality of metal pillars mounted on the routing layer through the corresponding pillar openings, a chip mounted on the first routing layer through the chip opening and a molding compound formed on the polyimide layer to encapsulate the metal pillars and the chip. The polyimide layer is used to control the warpage of the FOPLP. The polyimide layer is formed inside the FOPLP and the chip is directly mounted on the first routing layer through the chip opening, so a height of the FOPLP is not increased when the first PI layer is added.

Abstract: A method and apparatus for polishing a substrate is disclosed herein. More specifically, the apparatus relates to an integrated CMP system for polishing substrates. The CMP system has a polishing station configured to polish substrates. A spin rinse dry (SRD) station configured to clean and dry the substrates. A metrology station configured to measure parameters of the substrates. A robot configured to move the substrate in to and out of the SRD station. And an effector rinse and dry (EERD) station configured to clean and dry an end effector of the robot.

Abstract: A semiconductor device includes semiconductor elements, an insulating member, first and second terminals and control terminals. The semiconductor elements each include a semiconductor part, a first electrode on the back surface of the semiconductor part, a second electrode and a control electrode on the front surface thereof. The semiconductor elements are electrically connected in series and include first-end and second-end semiconductor elements each provided at an end of the series connection. The insulating member seals the semiconductor elements and includes a first surface and a second surface opposite to the first surface. The first and second terminals are electrically connected to the first electrode of the first-end semiconductor element and the second electrode of the second-end semiconductor element, respectively. Each control terminal is electrically connected to the control electrode.

Abstract: A layered bonding material 10 includes a base material 11, a first solder section 12a stacked on a first surface of the base material 11, and a second solder section 12b stacked on a second surface of the base material 11. A coefficient of linear expansion of the base material 11 is 5.5 to 15.5 ppm/K, the first solder section 12a and the second solder section 12b are made of lead-free solder, and both of a thickness of the first solder section 12a and a thickness of the second solder section 12b are 0.05 to 1.0 mm.

Abstract: A semiconductor device including an interposer including a central region and an edge region entirely surrounding the central region, wherein the interposer includes a wiring structure disposed in the first region and a metal structure disposed continuously within the entirety of the second region, a first semiconductor chip mounted in the central region and connected to the wiring structure, and a second semiconductor chip mounted in the central region adjacent to the first semiconductor chip and connected to the second wiring structure.

Abstract: Provided is a metal joint (5) including: a Ag—Cu—Zn layer (7); and Cu—Zn layers (6) joined to both surfaces of the Ag—Cu—Zn layer (7), wherein the Ag—Cu—Zn layer (7) has a composition in which a Cu component is 1 atm % or more and 10 atm % or less, a Zn component is 1 atm % or more and 40 atm % or less, and the balance is a Ag component with respect to the total 100 atm %, and wherein the Cu—Zn layers (6) have a composition in which a Zn component is 10 atm % or more and 40 atm % or less and the balance is a Cu component with respect to the total 100 atm %. It is therefore possible to obtain the metal joint (5), which is capable of joining metal base materials to each other without being limited to aluminum-based materials, and also have high mechanical strength.

Abstract: A structure including a wiring substrate, an interposer disposed on and electrically connected to the wiring substrate, a semiconductor die disposed on and electrically connected to the interposer, a first insulating encapsulation disposed on the interposer, a second insulating encapsulation disposed on the wiring substrate, and a lid is provided. The semiconductor die is laterally encapsulated by the first insulating encapsulation. The semiconductor die and the first insulating encapsulation are laterally encapsulated by the second insulating encapsulation. A top surface of the first insulating encapsulation is substantially leveled with a top surface of the second insulating encapsulation and a surface of the semiconductor die. The lid is disposed on the semiconductor die, the first insulating encapsulation and the second insulating encapsulation.

Abstract: A first semiconductor device and a second semiconductor device may be directly bonded using heterogeneous bonding layers. A first bonding layer may be formed on the first semiconductor device and the second bonding layer may be formed on the second semiconductor device. The first bonding layer may include a higher concentration of hydroxy-containing silicon relative to the second bonding layer. The second bonding layer may include silicon with a higher concentration of nitrogen relative to the first bonding layer. An anneal may be performed to cause a dehydration reaction that results in decomposition of the hydroxy components of the first bonding layer, which forms silicon oxide bonds between the first bonding layer and the second bonding layer. The nitrogen in the second bonding layer increases the effectiveness of the dehydration reaction and the effectiveness and strength of the bond between the first bonding layer and the second bonding layer.

Abstract: A semiconductor package includes a first redistribution substrate, a first semiconductor chip disposed on the first redistribution substrate, a first mold layer that covers the first semiconductor chip and the first redistribution substrate, a second redistribution substrate disposed on the first mold layer, a second semiconductor chip disposed on the second redistribution substrate, where the second semiconductor chip includes a second-chip first conductive bump that does not overlap the first semiconductor chip, a first sidewall that overlaps the first semiconductor chip, and a second sidewall that does not overlap the first semiconductor chip, wherein the first sidewall and the second sidewall are opposite to each other, and a first mold via that penetrates the first mold layer connects the second-chip first conductive bump to the first redistribution substrate, and overlaps the second-chip first conductive bump.

Abstract: Provided is a structure of a transistor, which enables a so-called normally-off switching element, and a manufacturing method thereof. Provided is a structure of a semiconductor device which achieves high-speed response and high-speed operation by improving on characteristics of a transistor, and a manufacturing method thereof. Provided is a highly reliable semiconductor device. In the transistor in which a semiconductor layer, source and drain electrode layers, a gate insulating layer, and a gate electrode layer are stacked in that order. As the semiconductor layer, an oxide semiconductor layer which contains at least four kinds of elements of indium, gallium, zinc, and oxygen, and has a composition ratio (atomic percentage) of indium as twice or more as a composition ratio of gallium and a composition ratio of zinc, is used.

Abstract: Provided herein are methods and related apparatus for purging processing chambers during an atomic layer deposition (ALD) process. The methods involve flowing purging gas from one or more accumulators to remove process gases from the processing chambers. Following the flowing of purging gas, additional reactants may be introduced into the processing chamber to continue an ALD cycle.

Abstract: A semiconductor package including a base chip; a semiconductor chip having a lower surface on which connection pads are disposed, the semiconductor chip being mounted on an upper surface of the base chip; a plurality of bumps on the connection pads and electrically connecting the base chip to the semiconductor chip; an adhesive film between the base chip and the semiconductor chip and fixing the semiconductor chip to the base chip; and an encapsulant on the base chip and encapsulating the semiconductor chip, wherein the semiconductor chip includes a central portion spaced apart from the upper surface of the base chip by a first distance, and an edge portion spaced apart from the upper surface of the base chip by a second distance, the edge portion being outside of the central portion, and a ratio of the second distance to the first distance is about 0.8 to about 1.0.

Abstract: Embodiments of the present disclosure provide a method of manufacturing a semiconductor structure. The semiconductor structure includes a peripheral area and an array area, and the method of manufacturing a semiconductor structure includes: providing a substrate; where the substrate in the peripheral area includes an active layer; a first isolation layer is further provided on the active layer; forming a buried word line in the substrate in the array area; where a second isolation layer is further provided on the buried word line; the buried word line includes a first conductive layer and a second conductive layer; patterning the first isolation layer and the second isolation layer by dry etching to form first through holes and a second through hole; where the first through holes expose a top surface of the active layer, and the second through hole exposes the second conductive layer.

Abstract: A semiconductor package includes a semiconductor chip, a lower redistribution layer disposed under the semiconductor chip, the lower redistribution layer including a plurality of lower insulating layers, a plurality of lower redistribution patterns, and a plurality of lower conductive vias, a lower passivation layer disposed under the lower redistribution layer and provided with a recess at a bottom surface of the lower passivation layer, an under bump metallization (UBM) pad disposed in the first recess, a UBM protective layer disposed in the first recess and connected to the lower conductive vias while covering a top surface and opposite side surfaces of the UBM pad, and an outer connecting terminal connected to a bottom surface of the UBM pad. The bottom surface of the UBM pad is positioned at a first depth from the bottom surface of the lower passivation layer.

Abstract: A radio frequency integrated circuit comprising: at least one transistor; a matching circuit coupled to said transistor; and at least one bump is used to form a passive element in said matching circuit, and said bump is used for radio frequency matching, the bumps can be used as passive components for amplifier harmonic impedance matching or the bumps can be the amplifier's passive components of the harmonic impedance matching, both of them can enhance the power, bandwidth and efficiency of amplifiers and integrated circuits.

Abstract: An image pickup apparatus includes: an image pickup member having a first surface and a second surface, an external electrode being disposed on the second surface; a terminal where a core wire terminal is disposed on a first upper surface and a core wire electrode is disposed on a lower surface; a wiring layer including an insulation layer and a wiring, the wiring being in contact with the external electrode and the core wire electrode, a third surface being in contact with the second surface and the lower surface; a resin layer disposed on the third surface, an outer dimension of the resin layer being equal to an outer dimension of the wiring layer, the resin layer fixing the image pickup member and the terminal; and an electric cable including a core wire bonded to the core wire terminal.

Abstract: A method for fabricating silicon die stacks for electron emitter chips by applying sintering to bind a silicon substrate die to other die layers. Metal powder is applied to the bonding surface of the die, covered with the chip carrier or chip and compressed between two heated plates. The bonding pads of the die may be conductively coupled to corresponding bonding pads of the other die layers.