Patents Examined by Jasmine J. Clark
  • Patent number: 11075152
    Abstract: A semiconductor package includes a first connection member including a first redistribution layer, a first frame disposed on the first connection member, a first semiconductor chip disposed on a first through-portion and having a connection pad, a first encapsulant covering a portion of each of the first frame and the first semiconductor chip and filling at least a portion of the first through-portion, a second connection member disposed on the first encapsulant and including a second redistribution layer, a second semiconductor chip disposed on the second connection member and having a second connection pad, a second encapsulant covering a portion of the second semiconductor chip, and a first through-via penetrating through the first frame, the first encapsulant, and a portion of the first connection member, and electrically connecting the first and second redistribution layers to each other.
    Type: Grant
    Filed: December 16, 2019
    Date of Patent: July 27, 2021
    Assignee: SAMSUNG ELECTRONICS CO., LTD.
    Inventors: Myung Sam Kang, Bong Ju Cho, Young Gwan Ko, Moon Il Kim
  • Patent number: 11075131
    Abstract: A semiconductor package including a semiconductor die, a molding compound and a redistribution structure is provided. The molding compound laterally wraps around the semiconductor die, wherein the molding compound includes a base material and a first filler particle and a second filler particle embedded in the base material. The first filler particle has a first recess located in a top surface of the first filler particle, and the second filler particle has at least one hollow void therein. The redistribution structure is disposed on the semiconductor die and the molding compound, wherein the redistribution structure has a polymer dielectric layer. The polymer dielectric layer includes a body portion and a first protruding portion protruding from the body portion, wherein the body portion is in contact with the base material and the top surface of the first filler particle, and the first protruding portion fits with the first recess of the first filler particle.
    Type: Grant
    Filed: August 22, 2019
    Date of Patent: July 27, 2021
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Yi-Da Tsai, Ching-Hua Hsieh, Chih-Wei Lin, Tsai-Tsung Tsai, Sheng-Chieh Yang, Chia-Min Lin
  • Patent number: 11075166
    Abstract: A microelectronic structure includes a microelectronic substrate having a first surface and a cavity extending into the substrate from the microelectronic substrate first surface, a first microelectronic device and a second microelectronic device attached to the microelectronic substrate first surface, and a microelectronic bridge disposed within the microelectronic substrate cavity and attached to the first microelectronic device and to the second microelectronic device. In one embodiment, the microelectronic structure may include a reconstituted wafer formed from the first microelectronic device and the second microelectronic device. In another embodiment, a flux material may extend between the first microelectronic device and the microelectronic bridge and between the second microelectronic device and the microelectronic bridge.
    Type: Grant
    Filed: August 27, 2020
    Date of Patent: July 27, 2021
    Assignee: Intel Corporation
    Inventors: Eric J. Li, Timothy A. Gosselin, Yoshihiro Tomita, Shawna M. Liff, Amram Eitan, Mark Saltas
  • Patent number: 11069608
    Abstract: A semiconductor structure includes first and second semiconductor dies bonded together. The first semiconductor die includes a first semiconductor substrate, a first interconnect structure disposed below the first semiconductor substrate, and a first bonding conductor disposed below the first interconnect structure and electrically coupled to the first semiconductor substrate through the first interconnect structure. The second semiconductor die includes a second semiconductor substrate and a second interconnect structure disposed below and electrically coupled to the second semiconductor substrate, and a through semiconductor via penetrating through the second semiconductor substrate and extending into the second interconnect structure to be electrically coupled to the second interconnect structure. The first bonding conductor extends from the first interconnect structure towards the through semiconductor via to electrically connect the first semiconductor die to the second semiconductor die.
    Type: Grant
    Filed: August 22, 2019
    Date of Patent: July 20, 2021
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Ming-Fa Chen, Sung-Feng Yeh, Tzuan-Horng Liu, Chao-Wen Shih
  • Patent number: 11071197
    Abstract: An electronic package including modulated mesh planes can reduce crosstalk between adjacent signal wires. Modulated mesh planes above and below a wiring plane include sets of adjacent wires arranged parallel to signal wires within the wiring plane, and sets of adjacent wires arranged perpendicular to the signal wires. The wires in each of the mesh planes are electrically interconnected and insulated from the signal wires by a dielectric layer. The electronic package also includes a region of the mesh planes having the adjacent wires that are perpendicular to the signal wires separated by a first distance, and another region of the mesh planes having adjacent wires perpendicular to the signal wires separated by a distance greater than the first distance. A set of rectangular mesh areas of the mesh planes can be populated with supplemental wires and via interconnect structures which can further reduce crosstalk.
    Type: Grant
    Filed: September 21, 2018
    Date of Patent: July 20, 2021
    Assignee: International Business Machines Corporation
    Inventors: Jinwoo Choi, Daniel M. Dreps, Yanyan Zhang
  • Patent number: 11063023
    Abstract: The present disclosure provides a semiconductor package, including a semiconductor die layer and a through insulator via (TIV). The semiconductor die layer has an active surface. The TIV is electrically coupled to the active surface. The TIV includes a body and a mesa. The body is surrounded by molding compound. The mesa has a tapered sidewall over the body. A portion of the tapered sidewall is covered by a seed layer.
    Type: Grant
    Filed: August 13, 2020
    Date of Patent: July 13, 2021
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY LTD.
    Inventors: Feng-Cheng Hsu, Jui-Pin Hung, Shin-Puu Jeng
  • Patent number: 11062998
    Abstract: A semiconductor package includes dies, a redistribution structure, a conductive structure and connectors. The conductive plate is electrically connected to contact pads of at least two dies and is disposed on redistribution structure. The conductive structure includes a conductive plate and a solder cover, and the conductive structure extend over the at least two dies. The connectors are disposed on the redistribution structure, and at least one connector includes a conductive pillar. The conductive plate is at same level height as conductive pillar. The vertical projection of the conductive plate falls on spans of the at least two dies.
    Type: Grant
    Filed: August 22, 2019
    Date of Patent: July 13, 2021
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Chung-Hao Tsai, Chen-Hua Yu, Chuei-Tang Wang, Wei-Ting Chen, Chien-Hsun Chen, Shih-Ya Huang
  • Patent number: 11056446
    Abstract: A semiconductor package device includes a wiring structure, a semiconductor chip and an encapsulant. The semiconductor chip is electrically connected to the wiring structure. The encapsulant is disposed on the wiring structure and covers the semiconductor chip. A roughness (Ra) of a surface of the encapsulant is about 5 nm to about 50 nm.
    Type: Grant
    Filed: August 21, 2019
    Date of Patent: July 6, 2021
    Assignee: ADVANCED SEMICONDUCTOR ENGINEERING, INC.
    Inventor: Wen-Long Lu
  • Patent number: 11049830
    Abstract: An input/output (I/O) interface of a die is disclosed. The I/O interface of the die includes a first region of a backside of the die. The I/O interface further includes a second region of the backside surface of the die positioned along at least a portion of a perimeter of the first region. The second region provides power and ground connections to the first region.
    Type: Grant
    Filed: August 14, 2019
    Date of Patent: June 29, 2021
    Assignee: International Business Machines Corporation
    Inventors: Chad Andrew Marquart, Daniel M. Dreps
  • Patent number: 11043471
    Abstract: A mixed-orientation multi-die (“MOMD”) integrated circuit package includes dies mounted in different physical orientations. An MOMD package includes both (a) one or more dies horizontally-mounted dies (HMDs) mounted horizontally to a horizontally-extending die mount base and (b) one or more vertically-mounted dies (VMDs) mounted vertically to the horizontally-extending die mount base. HMDs may include FPGAs or other high performance chips, while VMDs may include low performance chips and other physical structures such as heat dissipators, memory, high voltage/analog devices, sensors, or MEMS, for example. The die mount base of an MOMD package may include structures for aligning and mounting VMD(s), for example, VMD slots for receiving each mounted VMD, and VMD alignment structures that facilitate aligning and/or guiding a vertical mounting of each VMD to the die mount base.
    Type: Grant
    Filed: August 14, 2019
    Date of Patent: June 22, 2021
    Assignee: MICROCHIP TECHNOLOGY INCORPORATED
    Inventors: Justin Sato, Bomy Chen
  • Patent number: 11037878
    Abstract: The present application discloses a semiconductor device and a method for fabricating the semiconductor device. The semiconductor device includes a plurality of semiconductor memory dies vertically stacked through a plurality of microbumps; a plurality of through silicon vias positioned in the plurality of semiconductor dies and electrically coupled through the plurality of microbumps; and a plurality of protection liners positioned on sides of the plurality of through silicon vias; wherein the plurality of protection liners are formed of manganese-zinc ferrite, nickel-zinc ferrite, cobalt ferrite, strontium ferrite, barium ferrite, lithium ferrite, lithium-zinc ferrite, single crystal yttrium iron garnet, or gallium substituted single crystal yttrium iron garnet.
    Type: Grant
    Filed: April 16, 2020
    Date of Patent: June 15, 2021
    Assignee: NANYA TECHNOLOGY CORPORATION
    Inventor: Huan-Yung Yeh
  • Patent number: 11037894
    Abstract: Provided are a semiconductor device and a method of manufacturing the same. The semiconductor device includes a metal line layer on a semiconductor substrate, and a metal terminal on the metal line layer. The metal line layer includes metal lines, and a passivation layer having a non-planarized top surface including flat surfaces on the metal lines and a concave surface between the metal lines. The metal terminal is provided on the passivation layer. Opposite lateral surfaces of the metal terminal facing each other are provided on the flat surfaces of the passivation layer.
    Type: Grant
    Filed: July 8, 2020
    Date of Patent: June 15, 2021
    Assignee: SAMSUNG ELECTRONICS CO., LTD.
    Inventors: Jinchan Ahn, Won-young Kim, Chanho Lee
  • Patent number: 11024560
    Abstract: A semiconductor structure including a substrate, a dielectric layer, a conductive via, and a landing pad is provided. The dielectric layer is positioned on the substrate. The conductive via penetrates from a lower surface of the substrate to an upper surface of the dielectric layer. The landing pad is embedded in the conductive via.
    Type: Grant
    Filed: September 26, 2019
    Date of Patent: June 1, 2021
    Assignee: NANYA TECHNOLOGY CORPORATION
    Inventor: Hsih-Yang Chiu
  • Patent number: 11018070
    Abstract: A semiconductor die is provided. The semiconductor die includes a semiconductor substrate, an interconnection structure, conductive pads, a first passivation layer, and a second passivation layer. The interconnection structure is disposed on the semiconductor substrate. The conductive pads are disposed over and electrically connected to the interconnection structure. The first passivation layer and the second passivation layer are sequentially stacked on the conductive pads. The first passivation layer and the second passivation layer fill a gap between two adjacent conductive pads. The first passivation layer includes a first section and a second section. The first section extends substantially parallel to a top surface of the interconnection structure. The second section faces a side surface of one of the conductive pads. Thicknesses of the first section and the second section are different.
    Type: Grant
    Filed: August 22, 2019
    Date of Patent: May 25, 2021
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Jie Chen, Hsien-Wei Chen, Ming-Fa Chen
  • Patent number: 11004791
    Abstract: Various semiconductor chip metallization layers and methods of manufacturing the same are disclosed. In aspect, a semiconductor chip is provided that includes a substrate, plural metallization layers on the substrate, a first conductor line in one of the metallization layers and a second conductor line in the one of the metallization layers in spaced apart relation to the first conductor line, each of the first conductor line and the second conductor line has a first line portion and a second line portion stacked on the first line portion, and a dielectric layer that has a portion positioned between the first conductor line and a second line, the portion has an air gap.
    Type: Grant
    Filed: April 12, 2019
    Date of Patent: May 11, 2021
    Assignee: ADVANCED MICRO DEVICES, INC.
    Inventor: Richard Schultz
  • Patent number: 10998257
    Abstract: A semiconductor device includes a semiconductor body; an electrode provided on the semiconductor body and electrically connected to the semiconductor body; a first metal layer selectively provided on the electrode; an insulating layer surrounding the first metal layer on the electrode; and a second metal layer provided on the first metal layer. The insulating layer includes a first surface and a second surface adjacent to the first surface. The first surface contacts a top surface of the first metal layer at an outer edge of the first metal layer. The second metal layer has an outer edge contacting the second surface of the insulating layer.
    Type: Grant
    Filed: August 14, 2019
    Date of Patent: May 4, 2021
    Assignees: Kabushiki Kaisha Toshiba, Toshiba Electronic Devices & Storage Corporation
    Inventor: Tomohiro Taniguchi
  • Patent number: 10998294
    Abstract: A semiconductor package includes a plurality of stacked first semiconductor chips disposed over a substrate. At least a portion of the plurality of stacked first semiconductor chips is encapsulated in a first mold layer. The semiconductor package also includes a plurality of stacked second semiconductor chips disposed over the topmost chip of the stacked first semiconductor chips and the first mold layer. The semiconductor package also includes a third semiconductor chip disposed over the first mold layer and adjacent to the stacked second semiconductor chips. At least a portion of the third semiconductor chip overlaps with a portion of one or more of the stacked second semiconductor chips.
    Type: Grant
    Filed: August 13, 2019
    Date of Patent: May 4, 2021
    Assignee: SK hynix Inc.
    Inventor: Min Kyu Kang
  • Patent number: 10998225
    Abstract: The present disclosure provides a method for forming a semiconductor device. The method includes providing a substrate having a metal pattern, and forming an etch stop layer over the substrate. The etch stop layer includes a first material. The method also includes forming a diffused area in the etch stop layer by diffusing a second material from the metal pattern to the etch stop layer, and forming an insulative layer over the etch stop layer. The diffused area includes a lower etch rate to a first etchant than the insulative layer. A semiconductor device is also provided.
    Type: Grant
    Filed: January 16, 2019
    Date of Patent: May 4, 2021
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY LTD.
    Inventors: Tzu-Hui Wei, Chien-Hua Huang, Cherng-Shiaw Tsai, Chung-Ju Lee
  • Patent number: 10998262
    Abstract: An embedded multi-die interconnect bridge (EMIB) is fabricated on a substrate using photolithographic techniques, and the EMIB is separated from the substrate and placed on the penultimate layer of an integrated-circuit package substrate, below the top solder-resist layer. A low Z-height of the EMIB, allows for useful trace and via real estate below the EMIB, to be employed in the package substrate.
    Type: Grant
    Filed: April 15, 2019
    Date of Patent: May 4, 2021
    Assignee: Intel Corporation
    Inventors: Jiun Hann Sir, Poh Boon Khoo, Eng Huat Goh, Amruthavalli Pallavi Alur, Debendra Mallik
  • Patent number: 10998281
    Abstract: A package substrate of a semiconductor package includes second and third pad bonding portions respectively located at both sides of a first pad bonding portion disposed on a substrate body. First to third via landing portions are disposed to be spaced apart from the first to third pad bonding portions. First and second connection trace portions are disposed to be parallel with each other, and a first guard trace portion is disposed to be substantially parallel with the first connection trace portion. The second connection trace portion is connected to the first guard trace portion through a first connection plane portion, and the first connection plane portion connects the second connection trace portion to the second via landing portion. The third pad bonding portion is connected to the third via landing portion through a second connection plane portion.
    Type: Grant
    Filed: August 13, 2019
    Date of Patent: May 4, 2021
    Assignee: SK hynix Inc.
    Inventors: Jae Hoon Lee, Sun Kyu Kong, Ji Yeong Yoon