Abstract: A semiconductor package includes: a base chip; a first semiconductor chip disposed on the base chip; a second semiconductor chip disposed on the first semiconductor chip; a first insulating layer disposed between the base chip and the first semiconductor chip; a second insulating layer disposed between the first semiconductor chip and the second semiconductor chip; a first connection bump penetrating through the first insulating layer and connecting the base chip and the first semiconductor chip to each other; and a second connection bump penetrating through the second insulating layer and connecting the first semiconductor chip and the second semiconductor chip to each other. The base chip has a width greater than a width of each of the first and second semiconductor chips. The first insulating layer and the second insulating layer include different materials from each other.

Abstract: Systems and methods for a semiconductor device having an edge-notched substrate are provided. The device generally includes a substrate having a front side, a backside having substrate contacts, and an inward notch at an edge of the substrate. The device includes a die having an active side attached to the front side of the substrate and positioned such that bond pads of the die are accessible from the backside of the substrate through the inward notch. The device includes wire bonds routed through the inward notch and electrically coupling the bond pads of the die to the substrate contacts. The device may further include a second die having an active side attached to the backside of the first die and positioned laterally offset from the first die such that the second bond pads are accessible by wire bonds around the edge of the first die and through the inward notch.

Abstract: A semiconductor device structure and a method for manufacturing a semiconductor device. As a non-limiting example, various aspects of this disclosure provide a semiconductor device structure (e.g., a sensor device structure), and method for manufacturing thereof, that comprises a three-dimensional package structure free of wire bonds, through silicon vias, and/or flip-chip bonding.

Abstract: A semiconductor device assembly can include a substrate including a plurality of external connections. The assembly can include a first individual module and a first bond pad. The first individual module can be disposed on the substrate such that the first side of the first individual module faces the substrate. In some embodiments, the first individual module electrically is coupled to an external connection of the substrate via the first bond pad. The assembly can include a second individual module comprising a plurality of lateral sides. The second individual module can be disposed over the first individual module. In some embodiments, a first lateral side of the second individual module includes a first step forming a first overhang portion and a first recess. In some embodiments, the first bond pad is vertically aligned with the first recess of the second individual module.

Abstract: A method includes forming a first package structure including a first connection member including a first redistribution layer, a first frame having a first through-portion, a first semiconductor chip having a connection pad electrically connected to the first redistribution layer, and a first encapsulant covering a portion of each of the first frame and the first semiconductor chip, forming a second package structure including a second connection member including a second redistribution layer, a second semiconductor chip having a second connection pad, and a second encapsulant covering a portion of the second semiconductor chip, forming a first through-via, the first through-via electrically connecting to the second redistribution layer, and laminating the first package structure on the second package structure.

Abstract: A semiconductor package includes a package substrate, a lower semiconductor chip on the package substrate, an interposer on the lower semiconductor chip, the interposer including a plurality of pieces spaced apart from each other, an upper semiconductor chip on the interposer, and a molding member covering the lower semiconductor chip and the interposer.

Abstract: In various embodiments, a method for forming a bonded structure is disclosed. The method can comprise mounting a first integrated device die to a carrier. After mounting, the first integrated device die can be thinned. The method can include providing a first layer on an exposed surface of the first integrated device die. At least a portion of the first layer can be removed. A second integrated device die can be directly bonded to the first integrated device die without an intervening adhesive.

Abstract: A memory card includes an upper case, a lower case, and an integrated circuit package between the upper case and the lower case. The integrated circuit package includes a memory stacked chip on a panel substrate, and the memory stacked chip includes a base memory stacked chip and an additional memory stacked chip stacked on the base memory stacked chip. The integrated circuit package includes a frequency boosting interface chip on the panel substrate and electrically connected to the memory stacked chip, and a controller chip on the panel substrate and electrically connected to the memory stacked chip and the frequency boosting interface chip.

Abstract: A circuit substrate includes a base substrate, a plurality of conductive vias, a first redistribution circuit structure, a second redistribution circuit structure and a semiconductor die. The plurality of conductive vias penetrate through the base substrate. The first redistribution circuit structure is located on the base substrate and connected to the plurality of conductive vias. The second redistribution circuit structure is located over the base substrate and electrically connected to the plurality of conductive vias, where the second redistribution circuit structure includes a plurality of conductive blocks, and at least one of the plurality of conductive blocks is electrically connected to two or more than two of the plurality of conductive vias, and where the base substrate is located between the first redistribution circuit structure and the second redistribution circuit structure.

Abstract: Disclosed herein are structures and assemblies that may be used for thermal management in integrated circuit (IC) packages.

Abstract: A package substrate may include first conductive patterns, a first insulation layer and a second insulation layer. The first conductive patterns may be electrically connected with a semiconductor chip. The first insulation layer may be on an upper surface and side surfaces of each of the first conductive patterns. The first insulation layer may include at least one opening under at least one of side surfaces of the semiconductor chip. The second insulation layer may be on a lower surface of each of the first conductive patterns. Thus, a gas generated from the DAF may be readily discharged through the opening. A spreading of a crack, which may be generated at the interface between the side surface of the semiconductor chip and the molding member, toward the conductive patterns of the package substrate may be limited and/or suppressed. Adhesion between the semiconductor chip and the molding member may be reinforced.

Abstract: A semiconductor module includes a housing, a pin arranged in the housing and including a first contact region which has a press-fit connection, a semiconductor component arranged in the housing and electrically conductively connected to the pin, and a first substrate arranged in the housing and clamped in the housing via the pin by a non-positive locking connection, which, when formed, causes the press-fit connection to be deformed elastically and/or plastically with the first substrate. The first substrate has a first recess which is open and at least in part encompasses the pin in the first contact region. A metallic coating is applied to the first substrate at least in a region of the first recess so as to electrically conductively connect the first substrate to the semiconductor component, and a second substrate is in contact with the pin and connected within the housing in a non-releasable manner.

Abstract: An electronic device that has an antenna device that includes a conductive pattern layer comprising a first antenna element, the conductive pattern layer formed in an insulating substrate and adjacent to a first surface of the insulating substrate, and a second antenna element formed on a second surface of the insulating substrate opposite the first surface. The electronic device further has a semiconductor package that includes a redistribution layer (RDL) structure bonded and electrically connected to the conductive pattern layer, a first electronic component electrically connected to the RDL structure, and an encapsulating layer formed on the RDL structure and surrounding the first electronic component.

Abstract: A method includes forming a package, which includes forming a plurality of redistribution lines over a carrier, and forming a thermal dissipation block over the carrier. The plurality of redistribution lines and the thermal dissipation block are formed by common processes. The thermal dissipation block has a first metal density, and the plurality of redistribution lines have a second metal density smaller than the first metal density. The method further includes forming a metal post over the carrier, placing a device die directly over the thermal dissipation block, and encapsulating the device die and the metal post in an encapsulant. The package is then de-bonded from the carrier.

Abstract: A semiconductor package including a semiconductor chip, a lower redistribution layer under the semiconductor chip, the lower redistribution layer including a lower insulating layer at a central region and at a portion of an edge region, and a trench at a remaining portion of the edge region, a plurality of outer connecting terminals under the lower redistribution layer, a molding layer including a first molding section and the second molding section, the first molding section being on the lower redistribution layer and surrounding a side surface of the semiconductor chip and the second molding section being in the trench and contacting a side surface of the lower insulating layer, and an upper redistribution layer on the molding layer may be provided. The side surface of the lower insulating layer and a side surface of the second molding section may be coplanar with each other.

Abstract: A semiconductor die includes an interconnection structure, conductive pads, a first passivation layer, and a second passivation layer. The conductive pads are disposed over and electrically connected to the interconnection structure. The first passivation layer and the second passivation layer fill a gap between two adjacent conductive pads. The first passivation layer includes a first section and a second section. The first section extends substantially parallel to a top surface of the interconnection structure. The second section is connected to the first section. The second section is inclined with respect to a side surface of one of the conductive pads. Thicknesses of the first section and the second section are different.

Abstract: A package structure is provided. The package structure includes a substrate and a stack of semiconductor dies over the substrate. The package structure also includes an underfill element covering sidewalls of the semiconductor dies. The package structure further includes a protective film attached to the substrate and laterally surrounding the underfill element and the semiconductor dies. The underfill element separates the protective film from the semiconductor dies.

Abstract: Apparatuses relating generally to a microelectronic package having protection from interference are disclosed. In an apparatus thereof, a substrate has an upper surface and a lower surface opposite the upper surface and has a ground plane. A first microelectronic device is coupled to the upper surface of the substrate. Wire bond wires are coupled to the ground plane for conducting the interference thereto and extending away from the upper surface of the substrate. A first portion of the wire bond wires is positioned to provide a shielding region for the first microelectronic device with respect to the interference. A second portion of the wire bond wires is not positioned to provide the shielding region. A second microelectronic device is coupled to the substrate and located outside of the shielding region. A conductive surface is over the first portion of the wire bond wires for covering the shielding region.

Abstract: A semiconductor device includes a lead frame having a first principal surface which includes a recess, and a second principal surface opposite to the first principal surface, a relay board, disposed in the recess, and having a third principal surface, and a fourth principal surface opposite to the third principal surface, wherein the fourth principal surface opposes a bottom surface of the recess, a first semiconductor chip disposed on the third principal surface, a first conductive material connecting the lead frame and the relay board, and a second conductive material connecting the relay board and the first semiconductor chip. A distance between the second principal surface and the third principal surface is less than or equal to a distance between the second principal surface and the first principal surface.

Abstract: A structure including stacked substrates, a first semiconductor die, a second semiconductor die, and an insulating encapsulation is provided. The first semiconductor die is disposed over the stacked substrates. The second semiconductor die is stacked over the first semiconductor die. The insulating encapsulation includes a first encapsulation portion encapsulating the first semiconductor die and a second encapsulation portion encapsulating the second semiconductor die.