Abstract: A method and arrangement for converting an analog input signal into a digital output signal. The analog input signal is converted into a duty cycle modulated square wave. For reducing the communication rate of the digital output signal a time frame of subsampling periods is created and, within each subsampling period, the position of samples, which approximately coincide with the transients of the square wave, is determined. The invention further provides an image sensor comprising a plurality of such arrangements.

Abstract: A method and means for reducing high-duty-cycle unconstrained binary signal sequences in storage and communications processes and systems by invertibly mapping such sequences into a (1, k) rate ⅔ RLL codestream constrained to a duty cycle substantially approximating one-third. That is, binary sequences ordinarily mapping into high-duty-cycle RLL-code sequences are either inhibited from repeating indefinitely or excluded.

Abstract: An optical quantizer (10) that employs a chain of optical thresholding devices (16) positioned in the propagation path of an optical input beam (12) to be quantized. Each optical thresholding device (16) saturates and turns transparent if the intensity of the optical beam (12) that impinges it is above a predetermined threshold level designed into the device (16). If the input beam (12) saturates the optical thresholding device (16), the device (16) outputs an indicator signal (22) identifying the saturation. The input beam (12) propagates through the optical thresholding device (16) with some attenuation caused by the saturation, and impinges subsequent optical thresholding devices (16) in the chain. Eventually, the attenuation of the input beam (12) caused by the multiple saturations will decrease the beam intensity below the threshold level of the next optical thresholding device (16). The number of indicator signals (22) gives an indication of the intensity of the input beam (12).

Abstract: In the present invention is described a forward feed sigma delta modulator of higher order having automatic saturation detection and recovery. The modulator is separated into two parts which are connected together when there is no saturation, and disconnected when saturation is detected and recovery takes place. The first part contains an integrator and input output circuitry to allow continuous operation of the modulator. The second part contains additional integrators to provider for a higher order modulator and the saturation detector. The modulator can be constructed of single ended or differential switched capacitor technology, and there is a digital saturation detection scheme.

Abstract: An analog-to-analog converter uses programmable conversion arrays containing non-volatile memory cells to provide references that depend on the threshold voltages of the memory cells, with the type of conversion dependent on the threshold voltages of the cells. An analog input signal is applied to an analog-to-digital conversion array for conversion to a digital signal. The digital signal is applied to a digital-to-analog conversion array for conversion to an analog output signal. A memory cell in the digital-to-analog conversion array is selected corresponding to the digital signal and reads the memory cell to generate the analog output signal, which is equal to or has a one-to-one correspondence with the threshold voltage of the memory cell. The conversion arrays can be programmed with suitable threshold voltages to implement desired conversions, such as logarithmic conversion for voice applications or random conversions for signal encryption.

Abstract: A method and apparatus for digital to analog signal conversions with reduced noise include processing that begins by receiving a digital signal and filtering the digital signal to produce a filtered digital signal. The filtering is tuned to attenuate components of the digital signal having frequencies near one-half the sampling rate frequency and to pass other components of the digital signal having frequencies away from one-half the sampling rate frequency. The filtered signals are then converted to analog signals based on a clock signal having a sampling rate frequency and a voltage reference.

Abstract: The present invention provides a coding apparatus, decoding apparatus, coding-decoding apparatus and corresponding methods which easily generate an adaptive Huffman code. The coding apparatus includes a frequency counting element that counts the frequency of appearance of symbols in input data and a symbol selecting element that selects the data having a frequency larger than a predetermined threshold value as dominant symbol frequency data and transfers the dominant symbol frequency data to a code assigning element. The coding apparatus further includes a fixed code word memory that stores the Huffman codes prepared in advance and transfers them to the code assigning element as fixed code word data. The code assigning element generates the Huffman codes for the dominant symbols and synthesizes the Huffman codes and the fixed code word data stored in the fixed code word memory to obtain the Huffman code as a whole. The obtained Huffman code is stored in a code word memory.

Abstract: The invention provides methods and apparatus for improving the full-scale accuracy of an oversampling analog-to-digital converter. In particular, an improved switched-capacitor subtractor/integrator circuit is described that effectively provides a desired capacitor ratio by using N+M distinct unit capacitors that each sample an input signal a first predetermined number of times and sample one or more reference signals a second predetermined number of times, where the ratio of the first predetermined number to the second predetermined number is the desired capacitor ratio N/M.

Abstract: An analog-to-digital converter system 10 is provided that comprises two separate banks of capacitors that are configured with a single operational amplifier 30 for each stage 29 within the system 10. The banks of capacitors are used in an interleaved fashion to simultaneously digitize analog input voltages and sample a reference voltage V.sub.REF to enable the digitization of a gain error associated with the operation of amplifier 30. This gain error can be combined with the raw digital output of the converter using an arithmetic logic unit 18 to result in a calibrated output for the system 10.

Abstract: A low-power column parallel ADC architecture for image sensors that reduces the power consumption by reducing the number of switchings of a comparator to digitize a row of pixel data. Two ramp reference signals are provided in accordance with the principles of this invention. A first ramp signal is provided to each comparator that is clocked with an associated first clock signal. In each column comparator, the first ramp signal is compared to the pixel data using clock1, wherein clock1 corresponds to N multiple of a second clock signal (clock2), with N>1. Only when the column comparator detects a first crossover with the first ramp signal, then the comparator switches at every clock cycle of the second clock, clock2, to compare and detect a second crossover point with the second reference signal. This arrangement can greatly reduce the number of switchings required to digitize a row of pixel data, thereby resulting in significant power saving.

Abstract: What is disclosed is an apparatus for reducing row reset noise in photodiode based complementary metal oxide (CMOS) sensors. The apparatus uses at least one reference pixel for each row of pixels in a sensor array. Also, a reset noise elimination unit is provided to adjust the values received from the pixels in a particular row by an adjustment value determined from the reset values received from the reference pixels. Additionally, a method of using the apparatus is disclosed. The method has a step of providing a first reset signal to a row of pixels including the reference pixels. The method also reads out a first set of values from this row after integration. The method continues with providing a second reset signal to the row and a second set of values is read from the row. An adjustment value is calculated from the difference of the values which are read out from the reference pixels.

Abstract: A parallel pipelined analog-to-digital converter for use with chips containing large arrays of detectors is described. In these A/D converters, the degree of parallelism decreases between earlier and later pipeline stages. That is, there are fewer instances of at least one of the later stages than there are instances of at least one of the earlier stages. Thus, the instances of the earlier stages are responsible for processing a fewer number of pixels than are instances of the later stages. Viewed another way, the parallel pipelined analog-to-digital converter architecture of this invention assumes a tree or branched arrangement in which the earlier stages correspond to leaves and the later stage condense to branches. In an extreme example, the later stages coalesce to a single route.

Abstract: Digital self-calibration of digital-to-digital converters includes an approach to correct for the arbitrary errors in the analog section provided that there are sufficient redundancy in the architecture. The calibration procedure is performed off-line (upon power-up or user request). The digital correction technique avoids the need of a very accurate current mirror or an extra digital-to-analog converter as a standard transfer device.

Abstract: A method and system enables ADCs to be calibrated from reference signals with unknown parameters. A given analog reference signal s(t) is supplied to an ADC. The output (x(k)) of the ADC is used by calibration logic to estimate at least one parameter of the reference signal. A FIR filter accepts as input the x(k) signals and outputs an estimate (s(k)) as the sampled instances of the s(t) signal. A reconstruction table is created that approximates the analog input signal in the digital domain using the knowledge of the analog input signal waveform type. The actual ADC outputs are compared to the values in the reconstruction table to produce a correction table for calibration. A continuous time reference signal may be utilized for training the correction table. The method and system is data adaptive, so it may be applied, for example, with any sinusoidal reference input.

Abstract: A capacitive array particularly for converters, comprising a plurality of unitary capacitors, the number of the unitary capacitors being equal to 2.sup.n, where n is the number of bits of the binary code required in output, the unitary capacitors being mutually connectable so as to obtain capacitors in which the capacitance ratio between one capacitor and the adjacent parallel-connected capacitor is equal to a factor of two. The invention is that the factor-of-two capacitance ratio of adjacent capacitors is achieved by mutually diagonally connecting in parallel the unitary-capacitance capacitors of the capacitive array in a preset number according to the capacitance value to be obtained.

Abstract: An electronic device for converting an analog input signal into a digital output signal includes: a summing device for adding the analog input signal with a feedback analog signal and for generating a summer output signal representative of the sum of the analog input signal and the feedback analog signal; an analog filter coupled to the summing device for filtering undesired signal components from the summer output signal; an analog mixer receiving a signal having a first mixer frequency and coupled to receive the output of the analog filter for frequency translating the filtered summer output signal to a frequency translated summer output signal having one or more frequency components different than the input frequency; a quantizer coupled to the analog mixer for sampling the frequency translated summer output signal at a sampling frequency and for generating the digital output signal; and a feedback branch coupled between the quantizer and summing device for providing the feedback analog signal to the summi

Abstract: A computer-readable medium includes computer-executable instruction for compressing data to form a compressed data stream for a restricted channel. Specifically, data is compressed to form code values and character values, and a mask is created that indicates the location of these code values and character values in the compressed data stream. Each mask constructed by the method is selected from a set of valid values that can pass through the restricted channel.

Abstract: An analog-to-digital (A/D) converter for converting an analog signal into a digital signal includes a first resistor ladder coupled between a first reference voltage and a second reference voltage. The A/D converter also includes a second resistor ladder that matches the first resistor ladder and that has a first end and a second end coupled to an analog signal source. The first resistor ladder and the second resistor ladder are coupled to at least two comparators with each comparator having a reference input and an analog input. The impedance at each reference input due to the first resistor ladder matches the impedance at each corresponding analog input due to the second resistor ladder.

Abstract: A symbol decoding apparatus run-level-decodes corresponding symbol data using the same scan pattern data as used for run-level-encoding. A symbol separator separates the received run-level-encoded symbol data into run data and level data. An address outputter selects a particular scan pattern using the scan pattern data associated with the symbol data, and selects a scan address for storing the level data among the scan addresses corresponding to the selected scan pattern using the separated run data. A data store stores the level data supplied from the symbol separator at the storage position designated by the selected scan address. Thus, the run-level-encoded symbols are run-level-decoded based on the scan pattern used for run-level encoding and stored in a form appropriate for use in a downstream unit.

Abstract: A punctured maximum transition run (PMTR) code includes transition-allowed bit slots and transition-disallowed bit slots. Each of the transition-allowed bit slots is a bit slot in which a bit representing a third consecutive transition of a logic signal can occur whereas each of the transition-disallowed bit slots is a bit slot in which a bit representing a third consecutive transition of a logic signal cannot occur. There are at least two transition-allowed bit slots which are adjacent to each other. The transition occurs from a high logic level to a low logic level, or from a low logic level to a high logic level.