Abstract: In a semiconductor device, one ends of capacitors connected via switching elements to multiple-input terminals, the other ends of the capacitors being connected in common to an input terminal of a sense amplifier. A first power source is provided for supplying a power to the switching elements, and a second power source is provided for supplying a power to the sense amplifier. The first and second power sources are independent and separate.

Abstract: A data compression and decompression apparatus and method providing a high compression ratio. The data compressing apparatus includes, for example, an obtaining section, a first coding section, a first controlling section, a judging section, a second coding section, and a second controlling section. Characters are obtained one after another from a compression target. A code is then output corresponding to the character when the character and a predetermined number of characters are not identical. Subsequently, the number of characters obtained are counted when the character and the predetermined number of characters are identical, and a code corresponding to the number of characters counted is output when the character obtained is not identical with the predetermined number of characters.

Abstract: An encoder signal generating device in which a light receiving element (1) is constituted by a one-chip planar type phototransistor array that has a plurality of light receiving portions (21). Thus, this encoder signal generating device needs no amplification circuit. Even when using this encoder signal generating device as a device of the multi-channel type, the size of the light receiving element (1) is reduced, in comparison with that of a conventional light receiving element. Moreover, a highly sensitive encoder signal generating device, which has good S/N characteristics, is obtained.

Abstract: An improved key and keyboard arrangement for a compact word processor, the keyboard arrangement consisting of only twelve toggle keys with each key capable of seven functions, six of the keys being operated in a tactile manner by the finger tips of each hand. Additional keys are provided along a vertical edge adjacent to the twelve keys for operation by the users thumbs. A second embodiment includes a pair of similar keyboards hinged together, each keyboard having a single row of six toggle keys movable in six directions and a center depressable function, and a plurality of keys perpendicular to the six toggle keys located along a vertical edge adjacent to the six toggle keys, each of the six toggle keys having seven functions operated by tactile manipulation. The six toggle keys on each keyboard portion and the associated perpendicular keys represent all of the functions of one half of a standard QWERTY computer keyboard.

Abstract: An associative memory is utilized to perform LZW data compression. The respective locations of the memory contain a prefix code field and a character field. A register containing a code field and a character field is associatively compared to the locations of the memory to determine if a match exists therewith. If a match is found, the address of the match is inserted in the code field of the register and the next input character is inserted in the character field thereof. This process is continued until no match occurs. The code existing in the code field of the register is transmitted as the compressed code of the string and the contents of the register is written into the next empty location of the memory. A next cycle is initiated by nulling the code field of the register and repeating the described steps.

Abstract: A system which performs automatic gain control on received audio data. The system comprises an adjustable gain amplifier coupled to a gain control loop which is preferably a digital signal processor. The gain control loop comprises a zero-crossing detector which receives the audio output signal and generates a zero crossing output upon detection of a zero crossing. The gain control loop further comprises a gain adjustment scheduler which receives the zero crossing output and a gain adjustment signal. The gain adjustment scheduler advantageously adjusts the gain of the output signal in incremental steps near zero crossings so as to minimize distortion and the possibility of clipping of the input signal. The gain control loop further comprises a voice activity detector which detects substantial voice activity, wherein the automatic gain control system amplifies the audio input signal only during the substantial voice activity.

Abstract: A variable length decoder (VLD) for processing an input bit stream (e.g., MPEG video) which includes qualifying and non-qualifying types of variable length code words. The VLD includes an input circuit for receiving the input bit stream and providing a sequence of available input bits, a shifter circuit for providing a decoding window that includes one or more code words contained in the sequence of available input bits, a code word length decoding circuit for determining whether or not the decoding window contains a pair of qualifying code words, and for determining the combined length of the pair of qualifying code words and producing a combined length signal representative of the determined combined length, if the decoding window contains a pair of qualifying code words, and further, for determining the length of a leading code word contained in the decoding window and producing a leading word length signal representative of the determined length of the leading code word.

Abstract: For certain high-speed applications, where high-precision is not required analog-to-digital conversion may be performed by employing several comparators, each having their own offset. Each such comparator with an offset may be constructed by employing a differential amplifier with an offset followed by a conventional comparator. Advantageously, the time to obtain a conversion to digital of an analog sample is reduced in comparison to prior art converters, thus enabling high-speed operation.

Abstract: A multi-range analog-to-digital converter for encoding rundown times into a single channel of pulse width encoded data which may be conveyed to a remote equipment room over a single inexpensive, low quality digital cable. An input charge pulse is divided into multiple charge pulses and rundown times of the divided charge pulses are combined and encoded into a single channel of encoded data. A digital value representation of the input charge pulse is derived from the most accurate rundown times selected from the single channel of encoded data.

Abstract: A reduction in circuit size, an increase in operation speed, and a reduction in power consumption can be attained by a semiconductor device, in which capacitors are connected to multiple input terminals through switch, one terminal of each capacitance is commonly connected, and the common connection terminal is connected to a sense amplifier, including a reset at a floating point which is the contact between the common connection terminal of the capacitors and the input of the sense amplifier. In addition, an increase in yield can be realized by reducing the manufacturing cost.

Abstract: An analog-to-digital converter (ADC) formed on an integrated circuit chip from a plurality of cells includes a differential amplifier having first and second branches. The branches in each cell respectively have first and second transistors respectively responsive to an input voltage and an individual one of progressive fractions of a reference voltage. The relative outputs from the branches for each cell are dependent upon the relative values of the two voltages introduced to the cell. To minimize cell mismatches and the effects of these mismatches on cell outputs, first and second sets of averaging impedances, preferably resistors, are respectively connected between the output terminals of the first branch transistors, and between the output terminals of the second branch transistors, in successive pairs of cells.

Abstract: A method of transmitting an encoded file from a first computer system to a second computer system. The method utilizes a data dictionary having a number of entries. Each of the data dictionary entries contains an entry character array, an entry compression array, and an entry counter. Data packets are read into the memory and are encoded into the encoded file by using the data dictionary. The encoded file is then transmitted from the first system to the second system. The method also contains a decoding function wherein encoded packets received by the second system are decoded using the data dictionary.

Abstract: Two or more run-val mapping tables are selected to encode different subsets of video signals of a sequence of video signals. Each run-val mapping table is selected to map a particular set of run-val pairs to a corresponding set of run-val codes. Each run-val pair comprises a run and a val, the run corresponding to a length of a run of video signals having value zero and the val corresponding to a video signal having a non-zero value. Each run-val mapping table is used to generate a different part of an encoded bitstream for the sequence of video signals. The encoded bitstream is then decoded using the two or more selected run-val mapping tables. In a preferred embodiment, the selected run-val mapping tables are explicitly identified in the bitstream.

Abstract: In a method for transmitting digital data of images, etc., under the condition of n>m and k<n-m, when the synchronous data are not transmitted, the image data of "m" bits for the respective pixels are translated into the n-bit codes, of which identical logical bits do not continue more than or equal to "k" even if they are sequentially time-division multiplexed and transmitted with any combination, and then time-division multiplexed and transmitted. On the other hand, when the synchronous data are transmitted, the m-bit image data of the pixel is directly time-division multiplexed, and to this data, a serial code which is composed of "n-m" bits and including the specific bit string which is the continuous "k" bits of the identical logic is added. Thereby, making it possible to perform transmission and reception of the digital data and the synchronous data through one transmission line without a break of transmission or reception of the image data.

Abstract: The present invention provides a variable-length code decoder for inputting a code data bit string having a predetermined number of code data bits in every decoding cycle and decoding it, which comprises storing means for storing a decoded symbol and a node in a code tree in the next decoding cycle corresponding to each combination of a value of the code data bit string and a node in the code tree, reading means for reading the decoded symbol and the node in the code tree in the next decoding cycle from the storing means in accordance with the code data bit string inputted in a current decoding cycle and the node in the code tree in the current decoding cycle, outputting means for outputting the decoded symbol read by the reading means, and providing means for providing the node in the code tree in the next decoding cycle read by the reading means to the reading means.

Abstract: A ferroelectric transistor (72) is programmed with a gate voltage that shifts a threshold voltage of the ferroelectric transistor (72). The shifted threshold voltage generates a correction current (.DELTA.I.sub.(N-1)) in a combination circuit (52) that trims an output voltage of a DAC trim circuit (50). A ferroelectric material (32) of the ferroelectric transistor (72) stores a charge in accordance with a programming voltage and allows a dynamic adjustment of the correction current (.DELTA.I.sub.(N-1)) that is used to modify the output voltage of the DAC trim circuit (50).

Abstract: According to a data conversion method and apparatus, an original signal is wavelet-transformed with a desired expansion count to generate transformed data. The transformed data is corrected such that a difference between the original signal and a value obtained by inversely wavelet-transforming the transformed data falls within a desired tolerance range, thereby generating the corrected transformed data as compressed data in which the original signal is compressed.

Abstract: A demodulator subsystem incorporates second-order filtering for use within a sigma-delta DAC. A conventional demodulator is modified to include circuitry which manifests a second-order filtering response to the output of the demodulator. The added circuitry includes an additional pair of phased switched capacitor legs and a fixed capacitor. The combination of the additional circuitry with the existing phase switched and fixed capacitors of the conventional demodulator creates an additional pole which provides second order filtering to the demodulator output, effectively eliminating the high-order post filtering and minimizing both the circuit area required for implementation of the demodulator and its power consumption.

Abstract: In a pipeline type A/D converter, a switch for sampling an analog potential signal has its other terminal in connection with an A/D converter, a D/A converter, a capacitor for subtraction. Even when frequency of the analog potential signal is raised such that input current is increased and a voltage drop is increased at the switch, there will be no error in the result of subtraction like in the conventional example where analog potential signal was directly input to A/D converter. Accordingly, a pipeline type A/D converter with low power dissipation and satisfactory frequency characteristics is obtained.

Abstract: A majority logic circuit is supplied with output values of adjacent three comparators. The majority logic circuit outputs, as an output signal, the supplied three output values including at least two equal output values. Inverter circuits and AND circuits produce and output a read signal of an encoder which is a logical product between the output signal and an inverted signal of the output signal.