Abstract: A non-linear digital-to-analog converter (non-linear "DAC") and method are disclosed for scaling a digital input value by a non-integer and producing an analog output. The digital input value is multiplied by a non-integer, and the integer portion of the result is fed to a linear DAC to produce a linear analog output. At least one of the bits of the integer portion of the result is decoded, and at least one compensation value is generated responsive to the decoding. The compensation value is added to the linear analog output and represents the fractional portion of the result of scaling the digital input value by the non-integer. A method is also disclosed for utilizing the non-linear DAC for error compensation in a computer graphics system. Color intensity values are scaled up by a non-integer greater than one. A first analog output is generated proportional to the integer portion of the result.

Abstract: In this invention, in the case of transforming an input waveform signal into frequency components at a frequency component decomposing circuit 701 to allow the frequency components from the frequency component decomposing circuit 701 to undergo normalization and quantization, and encoding at a normalizing/quantizing circuit 702 and a code train generating circuit 703, operation of QMF is omitted with respect to bands of the unnecessary side by a processing band control circuit 704, whereby the number of operations necessary for filter operation is reduced so that high speed operation can be carried out and work area necessary for filter operation can be reduced. Namely, this invention can simplify filter operation in accordance with, e.g., required quality of reproduction signal, and can reduce circuit scale of encoding unit/decoding unit.

Abstract: A delta sigma modulator that has a low power dissipation without sacrificing modulator resolution includes, in one embodiment, a current mode digital to analog converter (DAC) in shunt with a conventional op amp in the first stage of the delta sigma modulator. By adding the current mode DAC in shunt with the first (or only) stage op amp of the delta sigma modulator, the slewing current needed during transients is provided by the combination of the op amp and DAC output signals. Since the DAC provides the slewing current required for the output signal change, the op amp need not apply the slewing current and therefore need only operate at low quiescent power.

Abstract: A decoder decodes input codes, such as Modified Huffman, Modified READ, and Modified Modified READ codes, and includes a zero bit detector which detects the number of consecutive leading zero bits of the input code. An address compressor forms address data by performing a logical operation of data indicating the number of detected zero bits and data excluding the consecutive leading zero bits and the next one bit of the data. A reference table for code conversion is addressed by the formed address data from the address compressor and outputs decoded data corresponding to the input code.

Abstract: Magnitudes of runs of constant signal value in signals representative of physical activities or objects are determined. The signals are converted to fixed-length run-length (RL) codes, wherein each long run in the signals that is longer than the largest run length represented by a single RL code is represented by at least one no-change RL code and an RL code representing a remainder value, wherein the no-change RL code represents a portion of the long run and also indicates that the immediately following RL code corresponds to a continuation of the long run. In a preferred embodiment, binary images are run-length encoded and the resulting run-length codes are subjected to variable-length encoding using structured Huffman tables.

Abstract: An improved decoding apparatus for a Manchester code receives an asynchronous Manchester code, synchronizes to a received clock signal, and decodes an output NRZ code and an output synchronous clock signal. A first decoding unit samples an asynchronous Manchester code by synchronizing the asynchronous Manchester code to a shift of a received clock signal to produce a synchronous Manchester code and a synchronous clock, and computes an NRZ code. A tolerance check unit receives the synchronous Manchester code and checks a tolerance with respect to a shift at a bit cell center of the synchronous Manchester code. A multiplexer unit receives the NRZ code and the synchronous clock signal and selectively outputs a multiplexed NRZ code and a multiplexed synchronous clock signal in accordance with a detection signal outputted from the tolerance check unit.

Abstract: The invention relates to a technique called "Internal Linear Feedback (ILF)" for the stabilization of high-order sigma-delta modulators. The ILF technique involves an overload detector and a selector. Once "overloaded" is detected by the overload detector, the selector is activated to make the modulator entering the ILF mode, in which additional internal linear feedback paths are employed to stabilize the modulator. Otherwise, the modulator operates in normal mode as a general high-order modulator.

Abstract: A digital-to-analog converter circuit is configured by a digital-to-analog converter receiving data of m bits (where `m` is an integer arbitrarily selected), a voltage-follower circuit containing an operational amplifier, a current-mirror circuit and a current-switching circuit. Herein, the data of m bits are extended by bits b.sub.H and b.sub.L in low-order positions thereof, wherein b.sub.H is placed in a higher order than b.sub.L. A noninverting input of the operational amplifier is connected to an output of the digital-to-analog converter; and a feedback resistor is connected between an inverting input and an output of the operational amplifier. The current-mirror circuit, using MOS transistors, provides two constant currents I.sub.H and I.sub.L in response to the bits b.sub.H and b.sub.L respectively, wherein a relationship between the constant currents I.sub.H and I.sub.L is defined by an equation of I.sub.H =2.times.I.sub.L.

Abstract: Data converting method and apparatus for forming an RLL code which can perform a control to eliminate a DC component without an increase in number of bits. Natural numbers m, n, d, k, and k, satisfy conditions such that m<n and d<k<k.sub.1, an input data sequence by binary codes is divided into blocks each consisting of m bits and is sequentially converted to code words every one or a plurality of blocks at a ratio of (m bits:n bits) by a predetermined conversion rule in a manner that after completion of the conversion, the number of bits "0" between neighboring bits "1" is equal to d in minimum and k in maximum.

Abstract: An analog-to-digital converter comprises the following elements. A reference voltage generation circuit is provided for dividing a reference voltage into a plurality of divided reference voltages having voltage levels different from each other. A plurality of comparators are provided, each of which has a first input terminal connected to an analog input line for fetching analog signals and a second input terminal connected to the reference voltage generation circuit for fetching a corresponding one of the divided reference voltages so as to compare the analog signals with the divided reference voltage. Each of the comparators has an output terminal through which an output digital signal is outputted.

Abstract: A high speed differential analog to digital converter (ADC) is provided. The high speed differential ADC includes a driver section, a comparator section and a decoder section. The driver section includes a pair of series connected resistor ladders. A positive phase and negative phase emitter follower transistor pair is connected to the pair of series connected resistor ladders. The positive phase and negative phase emitter follower transistor has a collector connected to a supply voltage and has an emitter coupled to a respective one of the pair of series connected resistor ladders. A respective positive phase and negative phase AC current source drives the base of the respective positive phase and negative phase emitter follower transistor. A reference DC current source is coupled to the base of the positive phase and negative phase emitter follower transistors for determining a range of the ADC. A current source transistor pair biases the emitter follower transistor pair.

Abstract: In the case of coding a plurality of signals which are not independent of e another, a selection of the suitable type of coding is made as a function of a similarity measure.According to one aspect of the invention, the similarity measure is determined by firstly coding one of the signals according to the intensity-stereo method and then decoding it in order to create a signal affected by coding error, whereupon the latter signal and the associated non-coded signal are transformed into the frequency domain. In the frequency domain, a selection or evaluation of the actually audible spectral components, as well as of the signal affected by coding error and of the associated signal not affected by coding error, is undertaken using a listening threshold which is determined by a psycho-acoustic calculation. Intensity-stereo coding is undertaken in the case of a high similarity measure, whereas otherwise a separate coding of the channels is performed.

Abstract: In a semiconductor integrated circuit device having an A/D converter incorporated therein, a plurality of input channels are provided and input analog signals supplied therefrom are respectively held by a plurality of sample-to-hold circuits. The analog signals are simultaneously sampled by using such a pipeline operation that a first sampling is performed so that an analog signal held by the first sampling is A/D-converted and a second sampling is performed so that an analog signal held by the second sampling is A/D-converted, and the plurality of sample-to-hold circuits.

Abstract: The digital information encoding device for high speed processing based on a QM-Coder, which comprises a context table storage means having a read/write context table storage portion for storing a plurality of storing data comprising a prediction symbol and a probability estimating data, comprises two port RAM, wherein a storing data stored in the context table storage portion at the address based on the context received at a read address input node AR is directly outputted to an arithmetic calculation means via a data output node DO.

Abstract: A direct digital frequency synthesizer is provided that solves the problems of spurious spectra and spectral enveloping. The output of the D/A converter is gated such that a signal to be filtered is connected to circuit ground during an initial noisy portion of the D/A conversion cycle and is connected to the output terminals of the D/A converter during a later portion of the D/A conversion cycle. The spurious spectral components attributable to noisy operation of the D/A converter may therefore be largely eliminated. Furtherore, gating the output signal in this manner produces a similar effect as a decimating filter, shifting the enveloping function such that the first null occurs at a higher frequency, for example 2fc instead of fc. At the Nyquist frequency therefore, the level of the output signal is down less than one dB compared to the output signal at the lowest frequency, producing a largely flat spectral response over the frequency range of interest.

Abstract: Source data each consisting of m-bits can be converted into conversion codes each consisting of n (>m) bits with ease, and reverse conversion thereof can be performed with ease. The code conversion and the reverse conversion can be characterized in terms of a series of tables.The current input source data and the next input source data are respectively taken in by registers. Whether or not the run length at a connecting portion between consecutive source data satisfies conditions is determined by a control unit, and a table to be used is selected to finally obtain a conversion code.

Abstract: A continuous-time tunable Gm-C architecture for a .DELTA..SIGMA. modulator includes a tunable resonator and a low bit rate, high sample rate quantizer connected in a feedback loop. The resonator shapes the quantization noise spectrum so that the bulk of the quantization noise occurs outside the signal spectrum. A tunable Gm cell tunes the resonator's resonant frequency to maximize the modulator's SNR. The tunable Gm cell includes a fixed Gm cell having transconductance G.sub.f, a current divider and a recombination circuit that together effectively multiply G.sub.f by a factor .alpha., where -1<=.alpha.<=1, without effecting the cell's common mode current I.sub.cm. A positive current source supplies I.sub.cm, while maintaining a common mode resistance of R/2 and a theoretically infinite differential mode resistance. Thus, the resonator's resonant frequency can be varied from DC to approximately 1 Ghz while maintaining a stable common mode operating point and improving the modulator's quality factor.

Abstract: A rob bit compensation system improves the accuracy of digital signals transmitted to a digital network, such as a telephone network, that employs rob bit signaling (RBS) wherein the network periodically robs a bit for its own use. The rob bit compensation system can be employed within the transmit subsystem of a digital modem connected with the digital network that periodically robs a bit every nth frame, where n is, for example, 6, 12, or 24. The system may also be employed in association with the communications path within a coder/decoder (codec) that transmits data to the digital network. A feedback system advises the rob bit compensation system as to which frames of outgoing digital data are to have a bit robbed therefrom by the digital network. The feedback system causes a quantity to be mathematically combined with the digital data corresponding with each RBS frame in order to enhance accuracy of the RBS frames.

Abstract: A method and apparatus for compressing a block of data using a shared dictionary. Data to be compressed is divided into subblocks which are each provided to a respective compressor in a plurality of compressors. The compressors cooperatively construct a dynamic compression dictionary and compress the subblocks in parallel using the dictionary. Compressed subblocks output by the compressors are concatenated to form a compressed block.

Abstract: A plurality of solid-state switches are provided in parallel with a main circuit switch. A main circuit current is detected by a first current detecting device. A current flowing in each of the plurality of solid-state switches is detected by a second current detecting device. Based on the detected currents of the first and second current detecting devices, the main circuit switch is commanded to open and each solid-state switch is commanded to close by a control circuit, when a fault is detected by a fault detecting circuit. At this point of the process when the main circuit switch is opened, when a commutation anomaly is detected by a commutation detecting circuit, the conducting status of each solid-state switch is maintained. When the commutation achieves a normal status, each solid-state switch is interrupted and circuit breaking, at the point the capability of each solid-state switch is exceeded, is prevented.