Abstract: A high speed differential analog to digital converter (ADC) is provided. The high speed differential ADC includes a driver section, a comparator section and a decoder section. The driver section includes a pair of series connected resistor ladders with a positive phase voltage source connected at the top and bottom of one of the pair of series connected resistor ladders and a negative phase voltage source connected at the top and bottom of the other one of the pair of series connected resistor ladders; both the positive phase voltage source and the negative phase voltage source including a predetermined first DC voltage value. At least one additional positive phase voltage source is connected to the one of the pair of series connected resistor ladders and at least one additional negative phase voltage source is connected to the other one of the pair of series connected resistor ladders. The additional positive phase and negative phase voltage sources include a predetermined second DC voltage value.

Abstract: There is disclosed an A/D conversion circuit comprising a first A/D converter for receiving an input signal of the A/D conversion circuit and providing a digital output signal, the first A/D converter having a restricted resolution, wherein the input signal passes through delay means to a first input of a subtraction stage. A first D/A converter operating on the output signal of the first A/D converter generates an analog output signal and feeds the analog output signal via an adding stage to a second and subtracting input of the subtraction stage, wherein the input signal of the first D/A converter passes through a correction algorithm unit to a second D/A converter. The output signal of the second D/A converter is fed to a second input of the adding stage, wherein the correction algorithm unit provides empirically determined data for D/A conversion correction. A low pass filter coupled to the output of the subtraction stage provides a low pass filtered and amplified output signal.

Abstract: In a subranging type A/D converter apparatus, the A/D converter apparatus executes A/D conversion by separating the A/D conversion into an A/D conversion of high-order bits and an A/D conversion of low-order bits in two steps, while feeding back a first control signal for executing the A/D conversion of the low-order bits according to results of the A/D conversion of the high-order bits. A digital logic circuit section executes decision of the A/D conversion to a control terminal of a switch group of a reference voltage generator circuit for generating a plurality of reference voltages via a feedback line provided in a plurality of voltage comparators provided with a plurality of differential amplifiers. Each of the differential amplifiers includes a plurality of transistors each for executing differential amplification. The plurality of differential amplifier transistors are arranged so as to be symmetrical with respect to the feedback line provided in each of the differential amplifiers.

Abstract: A syntax parsing apparatus produces an effective bit length used in a video decoder which decodes encoded bitstream data. The syntax parsing apparatus includes an input port for receiving encoded bitstream data, and a control command output port for storing data of a plurality of control commands and sequentially selects and outputs the data of each of the plurality of the control commands. A variable-length code table unit selects and outputs either the bitstream data received via the input port or a variable-length code corresponding to the received bitstream data according to the control command data supplied from the control command output port, and outputs a variable-length code length corresponding to the received bitstream data. A data store stores the selected data output from the variable-length code table unit in response to the control command data.

Abstract: A method and an apparatus are provided for generating an (4,20) RLL modulation code having a decreased detectible window width and an increased recording density ratio. The code's spectrum is concentrated in the low-frequency band, thereby improving the signal-to-noise ratio. In addition, the hardware of an encoder and a decoder can be easily implemented since the modulation code has a fixed codeword length.

Abstract: A compensation system is configured to improve the accuracy of digital signals that are communicated through a digital network by reducing loss from digital attenuation quantization (DAQ; digital pad quantization) and rob bit signaling (RBS). The combined DAQ/RBS compensation system can be employed within a transmitting modem connected to the digital network and is constructed as follows. In a first embodiment, a first adjustment mechanism combines a DAQ compensation quantity with each segment of the digital data, prior to transmission, in order to enhance accuracy of the received digital data. The value of the DAQ compensation quantity depends on feedback that is provided to the compensation system during a series of test transmissions.

Abstract: A method for pair-match Huffman transcoding a Huffman-encoded bit stream (e.g., an MPEG digital video bit stream) which includes a plurality of qualifying and non-qualifying types of variable length original code words to be processed by a variable length decoder (VLD) with two-word bit stream segmentation, wherein the VLD has a decoding, window N bits wide. The method includes the steps of pair-match Huffman transcoding at least selected ones of the qualifying types of code words to produce corresponding transcoded code words in such a manner that the combined length of any pair of the transcoded code words is .ltoreq.N. A device for implementing this method, as well as a high-performance variable length decoder with two-word bit stream segmentation which utilizes this method, are also disclosed.

Abstract: The invention relates to an oversampled high-order modulator, especially a sigma-delta modulator, comprising cascaded integrators in a number corresponding to the order of the modulator, a quantizer, and a negative feedback. The problem with the high-order modulator is that the modulator is locked in an unstable mode from which it should be restored without considerably interfering with the operation of the modulator. The invention achieves this by temporarily changing the value of the negative feedback to a direction which will restore the stable operation.

Abstract: A two's complement digital to analog converter (300) is for converting a two's complement binary value to an analog output current, and includes a control circuit (310) which generates controlled value bits, a digital to analog current converter (DACC) (320), and an augmenter (330). The DACC (320) generates a DACC analog current which is a portion of the analog output current and which has an absolute value which is related to the binary value of the controlled value bits. The augmenter (330), which is coupled to a most significant bit of the two's complement binary value, generates a portion of the analog output current by modifying the absolute value of the DACC analog current by a least significant bit current increment when the most significant bit indicates a negative value of the two's complement binary value.

Abstract: A digital signal processing method and apparatus in which no noise is produced when switching between an original sigma-delta modulated signal and a sigma-delta re-modulated signal obtained on sigma-delta modulation of the original sigma-delta modulated signal. In a digital signal processing device 1a, delay line 3 delays the original sigma-delta modulated signal from an input terminal 2 by a pre-set number of samples. A sigma-delta modulator 6 sets the first-stage feedback loop to next stage feedback loop gain ratio to an integer and outputs a sigma-delta re-modulated signal. A bit length converter 5 matcthes the amplitude level of the original sigma-delta modulated signal entering the sigma-delta modulator 6 to the amplitude level of a feedback signal to a first-stage integrator employed in the sigma-delta modulator 6. On reception of a switching control signal S.sub.

Abstract: A method of converting a series of m-bit information words to a modulated signal. For each information word from the series an n-bit code word is delivered. The delivered code words are converted to the modulated signal. The code words are distributed over at least one group of a first type and at least one group of a second type. For the delivery of each of the code words belonging to the group of the first type the associated group establishes a coding state of the first type. When each of the code words belonging to the group of the second type is delivered, a coding state of the second type is established which is determined by an information word belonging to the delivered code word. When one of the code words is assigned to the received information word, this code word is selected from a set of code words based on the coding state. The sets of code words belonging to the coding states of the second type are disjunct.

Abstract: A variable-length code decoder includes plural barrel shifters, each of which executes shift processing on inputted variable-length code data bit by bit from the 0 bit to (the bit number of a maximum length codeword -1). The barrel shifters, which are in number equal to the bit number of the maximum length codeword, are arranged in parallel connection. Plural storing devices are provided, each of which stores a pair of a decoded symbol and codeword length thereof corresponding to code data. Plural fetching devices are provided, each of which fetches the pair of the decoded symbol and the codeword length thereof in accordance with the code data outputted from each of the barrel shifters. Each of the fetching devices is connected to a respective barrel shifter and storing devices. A selecting device is provided for selecting a predetermined pair from plural pairs of the decoded symbol and the codeword length fetched by the plural fetching devices in an initial decoding process.

Abstract: Signal processing apparatus comprises at least one digital signal processing device mounted on a circuit board, for performing sample-based signal processing at a sampling frequency; and a switched mode power supply mounted on the circuit board, the switched mode power supply operating at a switching frequency derived from the sampling frequency of the digital signal processing device.

Abstract: The magnitudes of an input voltage and individual ones of progressive fractions of a reference voltage are compared to produce first and second output voltages. Each of the elements in a first logical network receives the first output voltage from an individual one of the comparators and the second output voltage from a comparator non-consecutive with (preferably 2 comparators removed from) such individual comparator. Signals from these elements pass to latches. The latches have assertion and negation outputs which pass to elements in a second logical network. When an individual one of the elements in the second logical network provides a particular output, it prevents the elements receiving outputs from comparators responsive to lower reference voltage fractions from providing the particular output.

Abstract: In a measurement device, a detector output signal indicative of a condition magnitude, e.g., radiation, pressure, temperature, etc, and a ramp signal are added, and the resulting analog summation signal is converted to a digital signal. The digital signal is sampled, integrated, and averaged over a sampling time corresponding to a predetermined sampling number, such as to achieve a condition measurement signal having reduced analog-digital conversion error.

Abstract: A position encoder system is provided, such system including a code wheel, a pair of sensors, a counter, and a processor capable of identifying the correlation between separately identified markings of the code wheel. The identified correlation is indicative of code wheel accuracy, and thus is used to correct error in any angular position determined using the code wheel.

Abstract: A partition decoder system for high definition video decoding receives an HD picture divided into a selected number of sections, each section including identification data including a start code. An FLD detects each start code and assigns a pointer. A selected number of partition decoders, corresponding to the selected number of sections, uses the pointers to select and decode a selected section of the HD picture. The selection is made according to a selected memory management scheme.

Abstract: Low-redundancy codes are increasingly being striven for, such codes thus inevitably requiring comparatively long code words. However, since the memory requirement for coding tables increases considerably with the length of the code words, the use of code tables is then no longer expedient. Instead, coding is then effected by selecting the optimum code word in each case from a plurality of different code words taking account of coding; prescriptions and spectral decisions. For this purpose, the maximum run length for each code word is also determined, inter alia, but the spectral decisions are decisive as long as the maximum run length does not exceed a predetermined maximum value. Provided that the end of one code word and the beginning of a succeeding code word have the same binary value, incorrect decisions in the selection of the optimum code word may arise in the region where the synchronizing pattern is keyed in.

Abstract: An analog-to-digital (A-D) conversion device includes a channel selector for selecting a plurality of analog signal input terminals. The analog-to-digital converter converts an analog signal selected and supplied by the channel selector into a digital signal. A control device controls the channel selector to operate in either a scan mode in response to a starting trigger for scan conversion or a single mode in response to receiving a starting trigger for single conversion.

Abstract: The present invention discloses a method, apparatus, and article of manufacture for compressing vector data. The vector data is normalized to create normalized vector data. A history buffer is searched for a longest matching vector data that matches the normalized vector data. The longest matching vector data is encoded by assigning a substitution code. The vector data is normalized by translating the vector data to an origin and scaling the vector data to a unit square. The substitution code includes a denormalization function, which converts the normalized vector data to vector data.