Abstract: The invention relates to a method for determining a geometrical object for modeling the geometry of a metal sheet forming stage (1) in a CAD system. According to said method, an operator is defined which links a first geometrical model with a second geometrical model. The link is associated with a method for physically modeling a treating process which transfers a forming stage (1) from a corresponding first state into a second state. When the first geometrical model is modified, the second geometrical model is automatically updated in accordance with the physical modeling concept. The physical modeling concept for forming stages is thereby integrated into the static geometrical model environment of a CAD system. The physical modeling method is a method for calculating a border line (3) of a forming stage in an initial state prior to a forming process from a geometry of the border line (3) in a resulting state after the forming process.

Abstract: To enable immediate and easy-to-understand confirmation of heat-dissipation capability only by entering shape data of a radiator without switching screens. Shape data input sections and a shape display section for a radiator, and a graph display section which displays the calculated result as a graph are adapted to be displayed on the identical screen of the screen device. The pattern diagram of a radiator shape and the result of heat-dissipation capability can be seen on the graph simultaneously only by entering the shape data of the radiator without switching the screen.

Abstract: A method and a corresponding software and a system for processing a charge distribution according to a spreading function and a predefined operation are described.

Abstract: A system and a method for checking consistency of a lock-step process while debugging a microcontroller code. A host device copies a partially copies a production microcontroller in an ICE (in-circuit emulation) to form a virtual microcontroller. The virtual microcontroller and the microcontroller simultaneously and independently run a microcontroller code for debugging purposes. The microcontroller residing on a test circuit includes a first memory and the virtual microcontroller residing in the ICE includes a second memory. A host computer copies a content of the first memory and a content of the second memory in the host computer memory when the execution of the code is halted. Software in the host device compares the content of the first memory and the content of the second memory for consistency.

Abstract: A computer-implemented method may include defining an input bus signal in a graphical block diagram model by associating the input bus signal with a first group of signals, at least two of the first group of signals having a different data type; defining an output bus signal in the graphical block diagram model by associating the second bus signal with a second group of signals, each of the second group of signals corresponding to one of the first group of signals; defining an input to a non-virtual operation block in the graphical block diagram model as the input bus signal; defining an output to the non-virtual operation block in the graphical block diagram as the output bus signal; and simulating an operation performed on the input bus signal by the non-virtual operation block, the operation being performed on each of the first group of signals and output to each of the second group of signals.

Abstract: A custom storage assembly design module automates design of a storage assembly by automatically generating a recommended layout based on a user defined storage location. The design module, which can be communicatively coupled to a remote communications device including a monitor, provides custom design options in view of the recommended layout for the storage assembly, and monitors the selection of custom design options to avoid violation of allowance rules for the defined storage location. The design module displays the storage assembly with currently selected custom design options and also associated pricing information throughout the design process.

Abstract: A reconfigurable control system based on duplication of cells, in which each of these cells corresponds to a place on a Petri graph, and in that the configuration models the topology of the associated Petri graph.

Abstract: In a graphical modeling environment, bus signals, which group a plurality of signals together for simplifying a model, include a partial or complete physical definition. Models are simplified by passing bus signals through graphical objects representing functional entities, without degrouping the bus signal. During simulation of the model, code can be generated for the bus signal having a complete definition independent of other components of the graphical model.

Abstract: A method, apparatus and system for building a filter is disclosed. In a particular embodiment, the filter is a finite impulse response (FIR) filter and a compiler suitable for implementing the FIR filter is described. The compiler includes a filter coefficient generator suitably arranged to provide a first set of filter coefficients corresponding to the desired FIR filter spectral response and a filter spectral response analyzer coupled to the filter coefficient generator for providing an expected FIR filter spectral response based in part upon the first set of filter coefficients. The compiler also includes a filter resource estimator coupled to the filter spectral response simulator for estimating an implementation cost of the FIR filter based upon the second set of filter coefficients as well as a filter compiler unit coupled to the resource estimator arranged to compile a FIR filter implementation output file.

Abstract: A method and system for using processor compatibility information to select a compatible processor for addition to a multiprocessor computer. A software program is executed on the multiprocessor computer to determine the number of current processors in the multiprocessor computer and the revision number of each processor. A software program that compares the revision numbers of the current processors with processor compatibility information is then executed to determine the revision numbers of processors that are compatible with all current processors.

Abstract: A system and method for assembling a mesh model for engineering analysis by a user is provided. The system includes a user computer system, a remotely located computer system and a data storage means. The method includes the steps of selecting a plurality of component parts having a best practice mesh model format and selecting a predetermined property for each of the selected component parts, wherein the predetermined property is selected from a best practice library stored on the data storage means. The method also includes the steps of determining if the mesh model for each of the selected component parts meets a predetermined mesh quality condition using a best practice mesh quality checking software program.

Abstract: Method system, and product from application of the method, for design of a subsonic airfoil shape, beginning with an arbitrary initial airfoil shape and incorporating one or more constraints on the airfoil geometric parameters and flow characteristics. The resulting design is robust against variations in airfoil dimensions and local airfoil shape introduced in the airfoil manufacturing process. A perturbation procedure provides a class of airfoil shapes, beginning with an initial airfoil shape.

Abstract: Sample-count feedback from bus functional models and a binary convergence algorithm are to generate optimal sampling values for an accelerator, or hardware assisted simulator. The simulator includes a bus functional model and a driver program. A software readable register maintains a count of a number of samples provided the simulator in execution of a transaction on the bus functional model. For each supported bus functional model, a sample count retrieved from the bus functional model and a last sampling value given the hardware assisted simulator is maintained, and a binary convergence algorithm applied to generate sampling values based on the last sampling value given to the hardware assisted simulator and the last actual sampling value used by a given bus functional model for a transaction.

Abstract: In an evaluation system for evaluating a target board produced for use with a microprocessor, an evaluation microcomputer is connected between the target board and an evaluation tool. In the evaluation microcomputer: an emulation circuit emulates functions of the microprocessor, and supplies an emulation result to the evaluation tool through an interface circuit; the interface circuit interfaces the emulation circuit with the evaluation tool; and a data storing circuit stores data relating to the microprocessor. The emulation circuit and the interface circuit are powered by the target board, and the data storing circuit is powered by the evaluation tool. Alternatively, when the interface circuit further has the function of the data storing circuit, the interface circuit is powered by the evaluation tool.

Abstract: A computer-implemented method for generating a computer model of one or more teeth by receiving a digital data set of meshes representing the teeth; creating a parametric representation of the digital data set; and displaying the computer model of the teeth using the parametric representation. The model can be modified or transmitted for viewing or for fabricating dental appliances.

Abstract: An apparatus, program product and method for coordinating the distribution of CPUs as among logically-partitioned virtual processors. A virtual processor may yield a CPU to precipitate an occurrence upon which its own execution may be predicated. As such, program code may dispatch the surrendered CPU to a designated virtual processor.

Abstract: A computer-implemented method generates a computer model of one or more teeth by receiving as input a digital data set of meshes representing the teeth; selecting a curved coordinate system with mappings to and from a 3D space; and generating a function in the curved coordinate system to represent each tooth.

Abstract: Disclosed is a complete SAT solver, Chaff, which is one to two orders of magnitude faster than existing SAT solvers. Using the Davis-Putnam (DP) backtrack search strategy, Chaff employs efficient Boolean Constraint Propagation (BCP), termed two literal watching, and a low overhead decision making strategy, termed Variable State Independent Decaying Sum (VSIDS). During BCP, Chaff watches two literals not assigned to zero. The literals can be specifically ordered or randomly selected. VSIDS ranks variables, the highest-ranking literal having the highest counter value, where counter value is incremented by one for each occurrence of a literal in a clause. Periodically, the counters are divided by a constant to favor literals included in recently created conflict clauses. VSIDS can also be used to select watched literals, the literal least likely to be set (i.e., lowest VSIDS rank, or lowest VSIDS rank combined with last decision level) being selected to watch.

Abstract: A system and method for designing stamping tools that produce parts of desired dimensions. The system and method compensate for post stamping deviations from the desired dimensions in the shape of the tools used to produce the parts. The compensated tools result in nearly ideal parts.

Abstract: Irregular volumes within one or more three-dimensional volume datasets are identified and extracted in response to criteria. The processing involves automatically finding a seed voxel or seed cell that meets the criteria and thus belongs to an irregular volume of interest, and then identifying cells related to the seed cell by one or more predetermined relationships that are therefore also to be grouped into that irregular volume. Information, which can be of any suitable type, identifying each such cell as being related to other cells and belonging to an irregular volume is stored in a suitable data structure. The location or similar neighborhood information and other data describing properties or attributes of the identified cell are also stored. Because the irregular volumes are extracted and pre-processed in this manner, operations including rendering them on a display and performing Boolean and arithmetic operations on them can readily be performed.