Abstract: An In-Circuit Emulation system. A real microcontroller (device under test) operates in lock-step with a virtual microcontroller so that registers, memory locations and other debugged data can be retrieved from the virtual microcontroller without disrupting operation of a real microcontroller. When an I/O read instruction is carried out followed by a conditional jump instruction dependent upon the I/O read data, the virtual microcontroller does not have adequate time to compute the jump address after receipt of I/O read data from the real microcontroller. Thus, when this sequence of instructions is detected, the virtual microcontroller pre-calculates the jump address and makes the jump decision after receipt of the I/O read data from the real microcontroller.

Abstract: The invention relates to a computer system and method for simulating transport phenomena in a complex system. The computer system comprises a logic interface that enables a user of the computer system to dynamically construct logic to customize simulation of the physical system, a means for converting the constructed logic into corresponding object-oriented code, a means for integrating the object-oriented code with the main simulation system which comprises a simulation data model and simulation algorithms, resulting in an integrated simulation system, and a means for executing the integrated simulation system.

Abstract: A method for performing an analysis of at least one logic stage in a netlist, which include one or more drivers, is provided. The method includes operations of generating at least one look-up table for an output transient current to be based on values of input and output voltages using data available from a cell library; synthesizing analytically at least one current source model, which includes a DC component and a plurality of parasitic capacitances, using the look-up table; simulating the logic stage using the current source model to model the drivers; and obtaining characteristics of the simulated logic stage. A system and a machine-readable medium for performing the method are also provided.

Abstract: A computer-implemented method may include defining an input bus signal in a graphical block diagram model by associating the input bus signal with a first group of signals, at least two of the first group of signals having a different data type; defining an output bus signal in the graphical block diagram model by associating the second bus signal with a second group of signals, each of the second group of signals corresponding to one of the first group of signals; defining an input to a non-virtual operation block in the graphical block diagram model as the input bus signal; defining an output to the non-virtual operation block in the graphical block diagram as the output bus signal; and simulating an operation performed on the input bus signal by the non-virtual operation block, the operation being performed on each of the first group of signals and output to each of the second group of signals.

Abstract: A method for predicting the contribution of silicon interstitials to n-type dopant transient enhanced diffusion during a pn junction formation is disclosed. Initially, fundamental data for a set of microscopic processes that can occur during one or more material processing operations are obtained. The fundamental data are then utilized to build kinetic models for a set of reactions that contribute substantially to an evolution of n-type dopant concentration and electrical activities. The kinetic models are subsequently applied to a simulator to predict temporal and spatial evolutions of concentration and electrical activity profiles of the n-type dopants.

Abstract: A network management system includes a fault diagnosis engine, a topology mapper, an impact analyzer and a help desk system. The topology mapper includes a discovery module, a memory, and a presentation module. The discovery module is constructed and arranged to discover network elements in a communications network. The memory constructed and arranged to store topology data received from the discovery module. The presentation module constructed and arranged to present data related to topology of the communication network.

Abstract: A peak current modeling method and system for modeling peak current demand of an integrated circuit (IC) block such as, e.g., a compilable memory instance. A current demand curve associated with the IC for a particular IC block event is obtained via simulation, for example. A defined time region associated with the particular IC block event is divided into multiple time segments, whereupon at least a first current value and a second current value for each time segment is obtained based on the current demand curve. Thereafter, the current demand curve is approximated, on a segment-by-segment basis, using a select approximate waveform depending on a relationship between the first and second current values.

Abstract: A method for emulating a system call includes making the system call by a first process in a first operating system (OS) for interacting with a second process, wherein the first OS is emulated in a second OS, spawning an agent process, wherein the agent process is a child process of the first process, implementing a functionality of the system call using a general mechanism in the second OS between the agent process and the second process, passing a result associated with the system call from the second process to the agent process using the general mechanism, and relaying the result from the agent process to the first process using a system call in the second OS, wherein the result is stored by the first process.

Abstract: A method for bounded model checking of arbitrary Linear Time Logic temporal properties. The method comprises translating properties associated with temporal operators F(p), G(p), U(p, q) and X(p) into property checking schemas comprising Boolean satisfiability checks, wherein F represents an eventuality operator, G represents a globally operator, U represents an until operator and X represents a next-time operator. The overall property is checked in a customized manner by repeated invocations of the property checking schemas for F(p), G(p), U(p, q), X(p) operators and standard handling of atomic propositions and Boolean operators.

Abstract: An emulator for emulating a wireless network comprised of a plurality of RF nodes is comprised of a programmable controller for emulating the movements of the plurality of RF nodes within an emulated space. The controller provides both information and control signals based on the emulated movements. A programmable logic core receives a plurality of signals from the plurality of RF nodes and emulates signal propagation based on the information from the controller. A plurality of signal generation and conversion cards are interposed between the programmable logic core and the RF nodes. The signal generation and conversion cards are responsive to the control signals. Because of the rules governing abstracts, this abstract should not be used to construe the claims.

Abstract: As fast and powerful commodity processors have been developed, it has become practical to emulate on platforms built using commodity processors the proprietary hardware systems of powerful older computers. High performance is typically a key requirement for a system even when built using emulation software. In a hardware design many special cases and conditions which may cause exceptions are detected by logic operating in parallel with the instruction execution. In software these checks can cost extra cycles of processor time during emulation of each instruction and be a significant detriment to performance. Avoiding some of these checks by relying upon the underlying hardware checks of the host system and then using a signal handler and special software to recover from these signals is a way to improve the performance and simplify the coding of the software emulation system.

Abstract: A device provides an interface for permitting a user to define a block diagram model that represents a system, linearizing at least a portion of the block diagram model, analyzing a linearization result of at least one block of the block diagram model to determine contribution information of the at least one block toward a linearization result of the block diagram model, and outputting information concerning a result of analyzing the linearization result.

Abstract: The invention relates to a method, an engineering system and a programming device which simplify the projection and/or configuration of a project which represents an automation device for controlling a technical facility. For this purpose, the project engineer simply deposits in a project references that indicate which project components have to be deposited. Copies of said project components are automatically made and are deposited in the project on the programming device. The invention reduces error-proneness and projection complexity.

Abstract: A method and system for using processor compatibility information to select a compatible processor for addition to a multiprocessor computer. A software program is executed on the multiprocessor computer to determine the number of current processors in the multiprocessor computer and the revision number of each processor. A software program that compares the revision numbers of the current processors with processor compatibility information is then executed to determine the revision numbers of processors that are compatible with all current processors.

Abstract: Method and systems for analyzing the linearization of a model in a modeling environment are disclosed. The modeling environment may provide tools for linearizing the model to generate a linear model. The modeling environment may also provide tools for analyzing the linearization of the model. The tools for analyzing the linearization of the model may inspect the linear model to determine whether the model is properly linearized. The results of the linearization may be provided to users so that the users are able modify the linearization result and have the model linearized again using the modified information.

Abstract: An electromagnetic field analysis apparatus includes an information input device configured to input information as to wirings and components of an analysis object and a modeling device configured to generate a simulation model of the analysis object based on the inputted information as to wirings and components of the analysis object. A model simplification device simplifies the simulation model into a simplified simulation model by dividing the analysis object according to the simulation model into a plurality of cells and thinning out, when a plurality of elements are included in a cell, the plurality of elements.

Abstract: A tape course generator produces tape course definitions for use in programming a CNC composite tape lamination machine. The tape course generator includes a reference surface parameterizer that maps a contoured surface onto a parametric reference surface, and a reference plane instantiator that maps the reference surface onto a reference plane. The tape course generator also includes a tape boundary plotter that plots a tape boundary, and a boundary mapper that maps the tape boundary and a ply boundary into the reference plane. In addition, the tape course generator includes an intersection locator that identifies intersections of the ply boundary and the tape boundary, and a tape course delimiter that defines tape cuts and determines which points in the reference plane are within a tape course. Moreover, the tape course generator includes a tape course transformer that maps the defined tape course back onto the contoured surface.

Abstract: The present invention provides for native execution of an application on a client using code segments transmitted from a server over a network. The server includes an application code source, and a server code segment manager. The server may also include an application code transformation manager if the code source is not in the native binary format of the client. The client includes a client code segment manager, a code cache linker and manager, a code cache, and a CPU. When the client seeks to execute an application, code segments are transmitted from the server to the client and are stored in the code cache. The CPU then executes the code segments natively. When a code segment branches to a segment not in the cache, control passes to the client code segment manager, which requests the needed code segment from the server code segment manager of the server.

Abstract: A temperature averaging thermal sensor is implemented in an integrated circuit such as a microprocessor. The temperature averaging thermal sensor monitors the temperature of the integrated circuit in a plurality of different locations across the integrated circuit, calculates an average temperature and generates an output to indicate that the average temperature of the integrated circuit has attained a pre-programmed threshold temperature. In a microprocessor implementation, the microprocessor contains a plurality of thermal sensors each placed in one of a plurality of different locations across the integrated circuit and an averaging mechanism to calculate an average temperature from the plurality of thermal sensors. Sense circuitry reads the programmable input values and generates an interrupt when the temperature of the microprocessor reaches a threshold temperature.

Abstract: A computer-implemented method may include defining an input bus signal in a graphical block diagram model by associating the input bus signal with a first group of signals, at least two of the first group of signals having a different data type; defining an output bus signal in the graphical block diagram model by associating the second bus signal with a second group of signals, each of the second group of signals corresponding to one of the first group of signals; defining an input to a non-virtual operation block in the graphical block diagram model as the input bus signal; defining an output to the non-virtual operation block in the graphical block diagram as the output bus signal; and simulating an operation performed on the input bus signal by the non-virtual operation block, the operation being performed on each of the first group of signals and output to each of the second group of signals.