Abstract: A combined in-circuit emulation system and device programmer. A pod assembly used in an in-circuit emulation system has both a real microcontroller used in the In-Circuit Emulation and debugging process as well as a socket that accommodates a microcontroller to be programmed (a program microcontroller). Programming can be carried out over a single interface that is shared between the microcontroller and the program microcontroller and which is also used to provide communication between the real microcontroller and the In-Circuit Emulation system to carry out emulation functions. In order to assure that the emulation microcontroller does not interfere with the programming process for a microcontroller placed in a programming socket, a special sleep mode is implemented in the emulation microcontroller. This sleep mode is activated by a process that takes place at power on in which the a reset line is released with a specified data line held in a logic high state.

Abstract: A method of generating simulation reports regarding an integrated circuit layout is provided. The method can include providing a plurality of control points associated with the integrated circuit layout. A single simulation of the plurality of control points can be performed. Detailed information from the single simulation can be stored in a database. Desired information can then be extracted from the database to generate the simulation reports.

Abstract: A debugger produces a display based on instructions executed by a circuit simulator or verification tool and on waveform data produced by the simulator or verification tool when executing the instructions. The instructions include a set of statements, each corresponding to a separate circuit signal generated by a circuit and each including a function defining a value of the circuit signal as a function of values of other circuit signals. The simulator evaluates the statements at various simulation times to compute signal values at those simulation times. The waveform data indicates signal values the simulator computes when evaluating the statements. The debugger display includes a set of statement event symbols, each corresponding to a separate evaluation of a statement and each positioned in the display to indicate a simulation time at which the simulator evaluated the statement.

Abstract: A method is disclosed for modeling and processing an asynchronous functional specification to provide an input to an architecture synthesis engine. The method includes the step of generating an initial task graph from the specification, the task graph having a number of executable tasks. Selected data and control connections are established between respective tasks in accordance with a specified set of rules to define some of the tasks to be deterministic, and other of the tasks to be non-deterministic. Each of the control connections is then marked, to provide an annotated task graph for use as an input to the architecture synthesis engine, the annotated task graph enabling the engine to employ specified scheduling techniques.

Abstract: A circuit simulator simulates a circuit described by a circuit logic model as having a set of clocked registers interconnected by un-clocked logic to produce waveform data indicating states of each circuit input signal and of each register output signal as functions of clock signal edge timing. The waveform data and the logic model are then processed to produce a temporal schema model characterizing the circuit's logic and behavior. A display based on the temporal schema model depicts circuit behavior using separate symbols to represent successive circuit input signal states and register output signal states at various times during the simulation. The same display also graphically depicts fan-in or fan-out logical relationships by which circuit input signal states and register output signal states influence register input signal states.

Abstract: A method for operating a data processing system to simulate a mixer having an RF port, a LO port, and an IF port. In the present invention, the signal leaving the IF port is approximated by: b2=f(a1,a3)+S22*a2 where S22 is a constant, a2 is a signal input to the IF port, a1 is a signal input to said RF port and a3 is a signal input to said LO port, and f ? ( a1 , a3 ) = ? i = o M ? ? j = o N ? C ij * a1 i * a3 j The coefficients Cij are constants that depend on said mixer design. These coefficients can be determined by measuring the b2 when a1 and a3 are single tone signals. In addition, the coefficients can be determined by simulating said mixer on a non-linear circuit simulator when a1 and a3 are single tone signals.

Abstract: Computer implemented techniques for edge correlation between design objects in computer-aided design systems are provided. According to one embodiment, a source edge is exported from a source CAD system into a data representation in a global scene. The global scene is imported into a target CAD system so that one or more candidate target edges can be identified. Once the candidate target edges are identified, they are exported into a data representation of a local scene. Through a series of techniques, which can include an edge overlap algorithm, a region containment algorithm, an edge containment algorithm, and an edge extension algorithm, non-overlapping candidate target edges are removed from the local scene until a correlated set of target edges is produced. Design features, such a round or chamfer operation, can then be performed in the target CAD system on the correlated set of edges, just as they are in the source CAD system.

Abstract: Methods, systems and computer program products are provided for simulating network traffic by filtering simulated network traffic utilizing known Ramsey numbers so as to provide a first predefined number of related messages to simulate buy messages and a second predefined number of unrelated messages to simulate browse messages. The first predefined number may correspond to a clique of order m specified by a selected known Ramsey number and the second predefined number may correspond to an independent set of order n specified by the known Ramsey number.