Abstract: According to one embodiment, a memory system includes a storage medium including a first cell transistor, a first data latch, and a second data latch; and a first controller. The first controller is configured to instruct to the storage medium to, after instructing the storage medium to write data into the first cell transistor and before completion of the writing of the data into the first cell transistor, suspend a process being performed to the first cell transistor, read data from the first data latch, read data from the second data latch, and read data from the first cell transistor.

Abstract: A semiconductor storage device includes a first memory cell electrically connected to a first bit line and a first word line, a second memory cell electrically connected to a second bit line and the first word line, and a first circuit configured to supply voltages to the first word line. During a reading operation to read a page of memory cells including the first memory cell and the second memory cell, the first circuit supplies a first voltage to the first word line while the first memory cell is selected as a read target during a first time period, and supplies a second voltage greater than the first voltage to the first word line while the second memory cell is selected as a read target during a second time period that is different from the first time period, and directly thereafter, supplies the first voltage to the first word line.

Abstract: A magnetoresistive memory device that stores data in the synthetic antiferromagnet (SAF) included in each spin-torque memory cell provides for more robust data storage. In normal operation, the memory cells use the free portion of the memory cell for data storage. Techniques for storing data in the reference portions of memory cells are presented, where an unbalanced SAF that includes ferromagnetic layers having different magnetic moments is used to lower the switching barrier for the SAF and allow for writing data values to the SAF using lower currents and magnetic fields than would be required for a balanced SAF.

Abstract: According to one embodiment, three bits stored in one memory cell of a nonvolatile memory correspond to three pages. In first page writing, a threshold voltage becomes within a first or second region base on a bit value. In second page writing, if being within the first region, it becomes within the first or fourth region; and if being within the second region, it becomes within the second or third region. In the third page writing, if being within the first region, it becomes within the first or sixth region; if being within the second region, it becomes within the second or seventh region; if being within the third region, it becomes within the third or eighth region; and if being within the fourth region, it becomes within the fourth or fifth region.

Abstract: A normally-off state of an OS transistor is maintained or an on-state current thereof is increased without additionally generating a positive potential or a negative potential. When data is written to a node connecting an OS transistor and a capacitor, a potential supplied to the other side of the capacitor is set to an L level, and when the data is retained, the potential is switched from the L level to an H level. In addition, a power switch for a volatile memory circuit is provided on a low power supply potential side so that the supply of a power supply voltage can be stopped. Accordingly, at the time of data retention, a source and a drain of the OS transistor can be set at a high potential, whereby the normally-off state can be maintained and the on-state current can be increased.

Abstract: A volatile memory device includes a memory cell array configured to be supplied with a first power supply voltage through a first power supply line, and configured to store data based on the first power supply line; and a peripheral circuit configured to be supplied with a second power supply voltage through a second power supply line, and configured to control the memory cell array based on the second power supply line, the peripheral circuit including a self timing pulse circuit configured to determine an operation timing of the peripheral circuit, the self timing pulse circuit configured to be supplied with the first power supply voltage through the first power supply line, and the self timing pulse circuit being configured to adjust the operation timing of the peripheral circuit according to the voltage level of the first power supply voltage.

Abstract: Systems, apparatuses and methods may provide for technology to determine a programmable eviction ratio associated with a storage device and convert a portion of a single-level cell region in the storage device into a multi-level cell region in accordance with the programmable eviction ratio. In one example, the amount of the portion converted into the multi-level cell region varies gradually as a function of percent capacity filled in the storage device.

Abstract: According to some aspects, a layered structure comprises a memory layer exhibiting magnetization perpendicular to a face of the memory layer, the memory layer configured to change a direction of the magnetization in response to application of a current thereto, a magnetic layer exhibiting magnetization parallel or antiparallel to the direction of the magnetization of the memory layer and comprising a plurality of ferromagnetic layers, one or more non-magnetic layers, and an antiferromagnetic material, wherein a first non-magnetic layer of the one or more non-magnetic layers is situated between a first ferromagnetic layer of the plurality of ferromagnetic layers and a second ferromagnetic layer of the plurality of ferromagnetic layers, and wherein the antiferromagnetic material contacts at least one of the first non-magnetic layer and the first ferromagnetic layer, and an intermediate layer formed from a non-magnetic material located between the memory layer and the magnetic layer.

Abstract: A nonvolatile semiconductor storage apparatus is provided. To a data node and a reference node, a first transistor and a second transistor are respectively connected. In a data state determining operation, in the case where voltage is applied to the data node and reference node, the first and second transistors operate as precharge transistors in a first operation mode, and operate as mirror transistors in a second operation mode. The first and second operation modes are switched.

Abstract: A double data rate synchronous dynamic random access memory includes a control circuit and an output driving circuit. The control circuit provides a first voltage, a second voltage, a third voltage and a fourth voltage. The output driving circuit couples to the control circuit and includes a pull-up circuit, a pad and a pull-down circuit. When a voltage of the pad rises from the fourth voltage to the first voltage, a voltage between a drain and a source of a second driving transistor in the pull-down circuit is between the third voltage and the fourth voltage. When a voltage of the pad falls from the first voltage to the fourth voltage, a voltage between a drain and a source of a first driving transistor in the pull-up circuit is between the first voltage and the second voltage.

Abstract: A method includes, in one aspect, performing a read operation on a wordline of a memory device, wherein the wordline comprises a plurality of cells that are expected to be in a first state; based on the read operation, identifying one or more of the plurality of cells that are determined to be in a second state that differs from the first state; encoding data using information pertaining to the identified cells to generate a codeword comprising a plurality of bits to be written to the wordline, with at least one of the plurality of bits, which are to be written to at least one of the identified cells, having a value corresponding to the second state; and writing the generated codeword to the wordline.

Abstract: A memory device includes a plurality of resistive memory cells and a plurality of word lines. Each resistive memory cell includes a resistive memory element, a first switching element electrically coupled in series with the resistive memory element, and a second switching element electrically coupled in series with the first switching element. The first switching element and the second switching element in each resistive memory cell is coupled to different ones of the word lines.

Abstract: Comparison circuitry includes a first memory that stores a list of data items, a second memory that stores a list of most-recently used ones of the data items, a first comparator that compares an input data item first to the ones of the data items in the second memory and, only in absence of a hit in the second memory, compares the input data item to the data items in the first memory. At least one additional comparator may operate in parallel with the first comparator to compare the input data item to respective data items in at least one additional second memory, and to compare the input data item to respective data items in the first memory in absence of a respective hit in the at least one additional second memory. A data communications system may include a decoder incorporating such comparison circuitry.

Abstract: A method of fabricating a memristive structure for symmetric modulation between resistance states is presented. The method includes forming a first electrode and a second electrode over an insulating substrate, forming an anode contacting the first and second electrodes, forming an ionic conductor over the anode, forming a cathode of the same material as the anode over the ionic conductor, forming a third electrode over the cathode, and enabling bidirectional transport of ions between the anode and cathode resulting in a resistance adjustment of the memristive structure, the anode and the cathode being formed from metastable mixed conducting materials with ion concentration dependent conductivity.

Abstract: A semiconductor memory device includes a resistive-type memory cell and a sense amplifier for reading data from the memory cell. First and second transistors connected in parallel between a first node connected to the memory cell and a second node connected to the sense amplifier. The first transistor has a size that is different from the second transistor. Each of the first and second transistors has a gate that is connected to a first voltage source. A switch circuit controls a conduction state between the first and second nodes via separate paths through the first transistor and the second transistor. The sense amplifier compares a first current supplied to the memory cell via the first path at a first timing and a second current supplied to the memory cell via the second path at a second timing different from the first timing.

Abstract: A voltage generator which generates an internal voltage based on a varying voltage derived from the internal voltage includes a feedback control circuit configured to variably transmit the varying voltage responsive to a control signal to generate a feedback voltage. A voltage generation circuit is configured to generate the internal voltage based on the feedback voltage.

Abstract: The semiconductor memory device includes: a memory unit having a plurality of memory blocks; a voltage supply circuit configured to generate a plurality of operating voltages and transmit the operating voltages to global word lines; and a pass unit coupled between respective local word lines of the plurality of memory blocks and the global word lines, and configured to couple the local word lines of a selected memory block to the global word lines in response to block select signals corresponding to the respective memory blocks, wherein the pass unit couples local word lines of an unselected memory block to the global word lines for a preset time and then isolates local word lines of the unselected memory block from the global word lines in response to the block select signals while coupling local word lines of the selected memory block to the global word lines.

Abstract: An example memory device includes a planar semiconductor substrate layer; a planar variable resistance layer disposed above the planar semiconductor substrate layer; a planar channel layer disposed above the planar variable resistance layer; and one or more gates positioned along a length of the memory device and above the planar channel layer, wherein each respective gate of the one or more gates is configured to direct at least a portion of a current flowing through a respective region of the planar channel layer positioned below the respective gate into a respective region of the variable resistance layer positioned below the respective gate in response to a voltage applied to the respective gate being greater than a threshold voltage.

Abstract: Methods, systems, and devices for operating a ferroelectric memory cell or cells are described. A ground reference scheme may be employed in a digit line voltage sensing operation. A positive voltage may be applied to a memory cell; and after a voltage of the digit line of the cell has reached a threshold, a negative voltage may be applied to cause the digit line voltages to center around ground before a read operation. In another example, a first voltage may be applied to a memory cell and then a second voltage that is equal to an inverse of the first voltage may be applied to a reference capacitor that is in electronic communication with a digit line of the memory cell to cause the digit line voltages to center around ground before a read operation.

Abstract: A magnetic element capable of generating and erasing a skyrmion, including a magnet shaped as a thin layer and including a structure surrounded by a nonmagnetic material; a current path provided surrounding an end region including an end portion of the magnet, on one surface of the magnet; and a skyrmion sensor that detects the generation and erasing of the skyrmion. With Wm being width of the magnet and hm being height of the magnet, a size of the magnet, with the skyrmion of a diameter ? being generated, is such that 2?>Wm>?/2 and 2?>hm>?/2. With W being width of the end region in a direction parallel to the end portion of the magnet and h being height of the end region in a direction perpendicular to the end portion of the magnet, the end region is such that ??W>?/4 and 2?>h>?/2.