Abstract: Embodiments include systems and methods for improving column selection functionality of memory circuits. Embodiments operate in context of memory bitcells having additional series pass gates (e.g., junction sharing transistors) coupled with a column select signal to form an integrated column select port. Such a column select port can provide each bitcell with column select functionality in a manner that has improved area and power performance over some conventional (added NOR or other logic) approaches. However, the added column select port can still tend to add area, add column select load, and degrade writability (e.g., due to certain charge-sharing effects). Some embodiments are described herein for addressing the area and column select load by sharing certain intermediate nodes among multiple, adjacent bitcells. Other embodiments can include additional ground-connected transistors in a manner that improves writability (e.g., and read noise margin) of the bitcell.

Abstract: Provided is a magnetic element capable of generating one skyrmion and erasing the one skyrmion. The magnetic element includes a magnet shaped like a substantially rectangular flat plate, an upstream electrode connected to the magnet in a width Wm direction of the magnet and made of a non-magnetic metal, a downstream electrode connected to the magnet in the width Wm direction to oppose the upstream electrode and made of a non-magnetic metal, and a skyrmion sensor configured to detect the skyrmion. Here, a width Wm of the substantially rectangular magnet is such that 3·?>Wm??, where ? denotes a diameter of the skyrmion, a length Hm of the substantially rectangular magnet is such that 2·?>Hm??, and the magnet has a notch structure at the edge between the upstream electrode and the downstream electrode.

Abstract: A magnetic sensor device for sensing an external magnetic field includes a plurality of MLU cells, each MLU cell having a magnetic tunnel junction including a sense layer having a sense magnetization freely orientable in the external magnetic field, a storage layer having a storage magnetization; and a tunnel barrier layer between the sense layer and the storage layer. The magnetic sensor device includes a stress inducing device configured for applying an anisotropic mechanical stress on the magnetic tunnel junction such as to induce a stress-induced magnetic anisotropy on at least one of the sense layer and the storage layer. The stress-induced magnetic anisotropy induced by the stress inducing device corresponds substantially to a net magnetic anisotropy of the at least one of the sense layer and the storage layer. The magnetic sensor device can be programmed easily and has improved sensitivity.

Abstract: A magnetic sensor cell includes a magnetic tunnel junction including a reference layer having a reference magnetization oriented parallel to the plane of the reference layer, a sense layer having a sense magnetization, and a tunnel barrier layer between the sense and reference layers. A magnetic device is configured for providing a sense magnetic field for aligning the sense magnetization. The sense layer magnetization is orientable between a direction parallel to the plane of the sense layer and a direction perpendicular to the plane of the sense layer when the sense magnetic field is provided. The magnetic sensor cell can be used for sensing an external magnetic field including a component oriented parallel to the plane of the sense layer and a component oriented perpendicular to the plane of the sense layer.

Abstract: According to some aspects, a layered structure includes a memory layer, a magnetization-fixed layer, and a tunnel insulating layer. The memory layer has magnetization perpendicular to a film face in which a direction of the magnetization is configured to be changed according to information by applying a current in a lamination direction of the layered structure. The magnetization-fixed layer has magnetization parallel or antiparallel to the magnetization direction of the memory layer and comprises a laminated ferripinned structure including a plurality of ferromagnetic layers and one or more non-magnetic layers, and includes a layer comprising an antiferromagnetic material formed on a first ferromagnetic layer of the plurality of ferromagnetic layers and situated between the first ferromagnetic layer and the non-magnetic layer. The tunnel insulating layer is located between the memory layer and the magnetization-fixed layer.

Abstract: Provided herein are a memory device and a method of operating the memory device. The memory device comprises a plurality of memory cells stacked along a pillar vertical to a substrate, a peripheral circuit configured to program and verifying memory cells coupled to a selected word line, among the memory cells, and a control logic configured to control the peripheral circuit so that a pass voltage applied to unselected word lines is adjusted depending on a location of the selected word line when the memory cells are verified.

Abstract: A memory device includes a first memory cell, a second memory cell, a third memory cell, a bitline sense amplifier, and a switch circuit. The first memory cell is connected to a first wordline and a first bitline. The second memory cell is connected to the first wordline and a second bitline. The third memory cell is connected to the first wordline and a third bitline. The bitline sense amplifier is connected to the third bitline. The switch circuit is connected to the first bitline, the second bitline, and the bitline sense amplifier. The switch circuit performs charge sharing between the first memory cell and the first bitline to generate a first reference voltage, and charge sharing between the second memory cell and the second bitline to generate a second reference voltage.

Abstract: A memory includes a memory cell that operates in response to an array supply voltage, and a corresponding pair of bit lines that are pre-charged to a periphery supply voltage prior to each access of the memory cell. A sense amplifier coupled to the bit lines operates in response to the periphery supply voltage. The periphery supply voltage is less than the array supply voltage to enable power savings within the memory. A first pair of transistors is configured to couple the sense amplifier to the bit lines during write accesses to the memory cell, thereby boosting the write voltages applied to the bit lines during a write operation. That is, the first pair of transistors is configured such that the sense amplifier pulls one of the bit lines toward the periphery supply voltage (and the other one of the bit lines toward the ground supply voltage) during write accesses.

Abstract: The present disclosure provides a storage cell or storage structure having a static RAM-like operational behavior while nevertheless providing non-volatile storage capability on a single bit basis. To this end, a non-volatile storage element, such as a ferroelectric transistor element, may be provided within an inverter structure so as to allow the storage of a logic state at any desired operational phase by increasing the voltage difference used for operating the inverter structure. In illustrative embodiments, the stored logic state may be re-established during a power-up event.

Abstract: A memory device includes a semiconductor layer with an in-plane polarization component switchable between a first direction and a second direction. A writing electrode is employed to apply a writing voltage to the semiconductor layer to change the in-plane polarization component between the first direction and the second direction. A reading electrode is employed to apply a reading voltage to the semiconductor layer to measure a tunneling current substantially perpendicular to the polarization direction of the in-plane polarization component. The directions of the reading voltage and the writing voltage are substantially perpendicular to each other. Therefore, the reading process is non-destructive. Thin films (e.g., one unit cell thick) of ferroelectric material can be used in the memory device to increase the miniaturization of the device.

Abstract: According to one embodiment, A level shifter includes a first circuit configured to generate a first signal, the first signal being inverted and delayed signal of a second signal, a NAND circuit including a first input terminal and a second input terminal, the second signal being input to the first terminal, the first signal being input to the second terminal, a first transistor, a first voltage being applied to a first terminal of the first transistor, a second terminal of the first transistor being connected to a third input terminal of the NAND circuit, a third signal which inverts the second signal being applied to a gate of the first transistor, a second transistor, a second voltage being applied to a first terminal of the second transistor, the second voltage being higher than the first signal, a gate of the second transistor being connected to an output terminal, a third transistor, the second voltage being applied to a first terminal of the third transistor, a second terminal of the third transistor b

Abstract: A semiconductor device includes a first circuit configured to generate a first voltage based on a first current, a second circuit that includes a first transistor of a first conductivity type having a first terminal, a second terminal, and a first gate, the second circuit configured to generate a second voltage based on a voltage difference between the first terminal and the second terminal, and a third circuit configured to compare the first voltage and the second voltage, and generate a third voltage for adjusting a substrate bias of the first transistor, based on the comparison result.

Abstract: Apparatuses and methods for providing a program voltage responsive to a voltage determination are described. An example apparatus includes a memory array comprising a plurality of access lines. The example apparatus further includes a memory access circuit coupled to the memory array. The memory access circuit is configured to, during a memory program operation, provide an inhibit voltage to the plurality of access lines. The memory access circuit is further configured to, during the memory program operation, provide a program voltage to a target access line of the plurality of access lines responsive to a determination that an access line of the plurality of access lines has a voltage equal to or greater than a threshold voltage. The threshold voltage is less than the inhibit voltage.

Abstract: An antifuse one-time programmable (OTP) semiconductor memory comprises a PN junction diode formed in an active area of a semiconductor substrate proximate metal-oxide-semiconductor (MOS) capacitor wherein MOS gate conductor and MOS channel region are of the same conductivity type. A vertical bipolar junction transistor (BJT) is present in each cell, comprising said PN junction diode and a semiconductor layer below said PN junction diode. In a programmed cell, BJT emitter, base and collector are connected to the bit line, word line and common collector terminal, respectively. In an unprogrammed cell, BJT is an open-base BJT.

Abstract: A memory device including a plurality of pins and a plurality of memory dies is provided. Each of the memory dies is coupled to the pins, and each of the memory dies includes a matching circuit and a core circuit. During a course of power-on, according to voltage levels of data pins or control pins, the matching circuit may be selected automatically an enabled one of memory dies. When the core enabling signal is enabled, the core circuit starts operating, and when the core enabling signal is disabled, the core circuit stops operating. When the core circuit of one of the memory dies is operating, the core circuits of the rest of the memory dies stop operating.

Abstract: Methods, systems, and devices for operating a ferroelectric memory cell or cells are described. A ground reference scheme may be employed in a digit line voltage sensing operation. A positive voltage may be applied to a memory cell; and after a voltage of the digit line of the cell has reached a threshold, a negative voltage may be applied to cause the digit line voltages to center around ground before a read operation. In another example, a first voltage may be applied to a memory cell and then a second voltage that is equal to an inverse of the first voltage may be applied to a reference capacitor that is in electronic communication with a digit line of the memory cell to cause the digit line voltages to center around ground before a read operation.

Abstract: A semiconductor device comprising a first supply voltage, a second supply voltage, different from the first supply voltage; and a switching circuit. The switching circuit comprises an input configured to receive an input signal corresponding to the first supply voltage and an output configured to output an output signal corresponding to the second supply voltage. The switching circuit is a combined latch with a built-in level shifter that provides latching functionality and level shifting functionality and a leakage path is cut-off when the switching circuit is providing latching functionality.

Abstract: A disclosed example determines programmed states of a plurality of memory cells based on a counter reaching a trigger count value, the trigger count value selected from a plurality of different trigger count values based on a characteristic of the memory cells; determines, based on the programmed states, first ones of the memory cells that do not satisfy a target threshold voltage; and performs the programming pass on the first ones of the memory cells.

Abstract: A one-time programmable (OTP) latch includes a memory cell having a first non-volatile (NV) resistive element and a second NV resistive element, cross-coupled inverter circuitry, a first transistor having a first current electrode coupled to a first node of the cross-coupled inverter circuitry and a second current electrode coupled to a first terminal of the first NV resistive element, and a second transistor having a first current electrode coupled to a second node of the cross-coupled inverter circuitry, different from the first node, and a second current electrode coupled to a first terminal of the second NV resistive element. The OTP latch also includes write circuitry coupled to the memory cell and configured to program only one of the first NV resistive element or the second NV resistive element to an OTP state while the cross-coupled inverter circuitry is isolated from the memory cell by the first and second transistors.

Abstract: A semiconductor device includes: a source line; a bit line; a word line; a memory cell connected to the bit line and the word line; a driver circuit which drives a plurality of second signal lines and a plurality of word lines so as to select the memory cell specified by an address signal; a potential generating circuit which generates a writing potential and a plurality of reading potentials to supply to a writing circuit and a reading circuit; and a control circuit which selects one of a plurality of voltages for correction on a basis of results of the reading circuit comparing a potential of the bit line with the plurality of reading potentials.