Abstract: Various embodiments for inhibiting the programming of memory cells coupled to unselected bit lines while programming a memory cell coupled to a selected bit line in a flash memory array are disclosed. Various embodiments for compensating for leakage current during the programming of memory cells coupled to a selected bit line in a flash memory array also are disclosed.

Abstract: This technology provides a method for fabricating an electronic device. A method for fabricating an electronic device including a variable resistance element, which includes a free layer having a variable magnetization direction; a pinned layer having a first non-variable magnetization direction, and including first ferromagnetic materials and a first spacer layer interposed between adjacent two first ferromagnetic materials among the first ferromagnetic materials; a tunnel barrier layer interposed between the free layer and the pinned layer; a magnetic correction layer having a second magnetization direction which is anti-parallel to the first magnetization direction; and a third spacer layer interposed between the magnetic correction layer and the pinned layer, and providing an anti-ferromagnetic exchange coupling between the magnetic correction layer and the pinned layer.

Abstract: Sense circuits and methods to vary, in response to temperature, a precharge voltage level of a sense node during a sense operation, a sense node develop time during the sense operation, and/or a ratio of a deboost voltage level capacitively decoupled from the sense node to a boost voltage level capacitively coupled to the sense node during the sense operation.

Abstract: A semiconductor device includes a command input circuit and an internal command generation circuit. The command input circuit is synchronized with a clock signal to generate an input command which is enabled if an external command is inputted to the command input circuit. The internal command generation circuit delays the input command by a predetermined period according to a latency information signal to generate an internal command, in synchronization with a first division clock signal and a second division clock signal generated by division of a frequency of the clock signal. The predetermined period is set to be equal to a sum of a first delay amount corresponding to “N” times a cycle time of the second division clock signal and a second delay amount corresponding to “M” times a cycle time of the clock signal.

Abstract: A level shifter and dynamic random-access memory that includes a first output terminal and a second output terminal. A first voltage or a third voltage is outputted from the first output terminal. A second voltage or a fourth voltage is outputted from the second output terminal. The second voltage is lower than the first voltage. The third voltage is lower than the first voltage and higher than the second voltage. The fourth voltage is lower than the first voltage and higher than the third voltage.

Abstract: Systems and methods for managing data retention in a solid-state storage system utilizing data retention flag bytes are disclosed. A data storage device includes a non-volatile memory comprising a plurality of non-volatile memory devices and a controller configured to write data to a memory unit of the non-volatile memory array and write a data retention flag value indicating a number of bits of the written data programmed in a first of a plurality of logical states. The controller is further configured to read the data and determine a number of bits having the first of the plurality of logical states in the read data, and determine a difference between the number of bits of the written data programmed in the first logical state and the number of bits having the first logical state in the read data. The difference is used to determine data retention characteristics of the non-volatile memory.

Abstract: A controlling method of a semiconductor device provided with a memory array including a plurality of complementary cells, each cell including a first memory element and a second memory element, for holding binary data depending on a difference of threshold voltage therebetween, the controlling method comprising: performing a prewrite procedure that writes ‘0’ or ‘1’ to both of the first memory element and the second memory element.

Abstract: Ferroelectric-modulated Schottky non-volatile memory is disclosed. A resistive memory element is provided that is based on a semiconductive material. Metal elements are formed on a semiconductive material at two places such that two semiconductor-metal junctions are formed. The semiconductive material with the two semiconductor-metal junctions establishes a composite resistive element having a resistance and functions as a relatively fast switch with a relatively low forward voltage drop. Each metal element may couple a terminal to the resistive element. To provide a resistive element capable of being a resistive memory element to store distinctive memory states, a ferroelectric material is provided and disposed adjacent to the semiconductive material to create an electric field from a ferroelectric dipole. The orientation of the ferroelectric dipole changes the resistance of the resistive element to allow it to function as a resistive memory element.

Abstract: Embodiments of the invention are directed to a magnetic tunnel junction (MTJ) storage element having a reference layer formed from a reference layer material having a fixed magnetization direction, along with a free layer formed from a free layer material having a switchable magnetization direction. The MTJ is configured to receive a write pulse having a write-pulse and spin-transfer-torque (WP-STT) start time, a WP-STT start segment duration and a write pulse duration. The WP-STT start segment duration is less than the write pulse duration. The fixed magnetization direction is configured to form an angle between the fixed magnetization direction and the switchable magnetization direction. The angle is sufficient to generate spin torque electrons in the reference layer material at the WP-STT start time. The spin torque electrons generated in the reference layer material is sufficient to initiate switching of the switchable magnetization direction at the WP-STT start time.

Abstract: Memristor cell read margin enhancement employs programming switched memristor sub-bits of a memristor cell with a first resistive state to increase a relative read margin of the memristor cell. The switched memristor sub-bits of the memristor cell are connected in series. The read margin of the memristor cell is increased relative to a read margin of either of the switched memristor sub-bits.

Abstract: A semiconductor device includes a first memory mat (1L) including a plurality of split type memory cells (250L), a second memory mat (1R) including a plurality of split type memory cells (250R), a first control gate line (CGL) connected to a control gate (CG) of a split type memory cell (100L), and a second control gate line (CGR) connected to a control gate (CG) of a split type memory cell (100R). The semiconductor device further includes a first memory gate line (MGL) connected to a memory gate (MG) of the split type memory cell (100L), and a second memory gate line (MGR) connected to a memory gate (MG) of the split type memory cell (100R).

Abstract: A non-volatile memory system implements a multi-pass programming process that includes separately programming groups of memory cells in a common block by performing programming for memory cells that are connected to two adjacent word lines and are part of a first group of memory cells followed by performing programming for other memory cells that are also connected to the two adjacent word lines and are part of a second group of memory cells.

Abstract: Provided is a power switch circuit that includes a first level shifter that, in response to execution of a programming operation of a one-time programmable (OTP) memory cell array, turns on a first switching device that has received a supply voltage from an external supply voltage pad. The power switch circuit also include a second level shifter that, in response to execution of the programming operation, turns on a second switching device connected to the first switching device, to provide the supply voltage to the OTP memory cell array. The power switch circuit further includes a third level shifter that, in response to execution of a read operation of the OTP memory cell array, turns on a third switching device to provide a power voltage, which is internally generated within the power switch circuit, to the OTP memory cell array.

Abstract: The present disclosure includes apparatuses and methods for partitioned parallel data movement. An example apparatus includes a memory device that includes a plurality of partitions, where each partition of the plurality of partitions includes a subset of a plurality of subarrays of memory cells. The memory device also includes sensing circuitry coupled to the plurality of sub arrays, the sensing circuitry including a sense amplifier. A controller for the memory device is configured to direct a first data movement within a first partition of the plurality of partitions in parallel with a second data movement within a second partition of the plurality of partitions.

Abstract: To provide a magnetic element which can generate a skyrmion, and a skyrmion memory which applies the magnetic element or the like. To provide a magnetic element with a chiral magnet for generating a skyrmion, the chiral magnet is made of a magnetic material having a ?-Mn type crystal structure. Also, to provide a magnetic element with a chiral magnet for generating a skyrmion, the chiral magnet is made of a magnetic material having an Au4Al type crystal structure.

Abstract: A memory device includes a plurality of resistive memory cells and a plurality of word lines. Each resistive memory cell includes a resistive memory element, a first switching element electrically coupled in series with the resistive memory element, and a second switching element electrically coupled in series with the first switching element. The first switching element and the second switching element in each resistive memory cell is coupled to different ones of the word lines.

Abstract: A semiconductor memory device includes: a high frequency signal control unit for receiving an external command address signal, removing noise and glitch from the external command address signal and outputting a first command address signal; a pulse width control unit for controlling a pulse width of the first command address signal or maintaining the pulse width of the first command address signal and outputting a second command address signal with a predetermined pulse width; a refresh operation control unit for generating a row address for a refresh operation in response to the second command address signal; and a memory cell array for performing the a refresh operation in response to the row address.

Abstract: A test mode setting circuit may include: a first test mode signal generation unit operated by a first supply voltage, and suitable for activating a first test mode signal at a first voltage level in a state where mode setting is being performed, the first test mode signal corresponding to a test code among a plurality of first test mode signals; and a second test mode signal generation unit operated by a second supply voltage, and suitable for latching the first test mode signal at a second voltage level and generating the latched first test mode signal as a second test mode signal even when the first supply voltage is deactivated to a third supply voltage lower than the first supply voltage.

Abstract: To provide a semiconductor device equipped with anti-fuse memory cells, which is capable of improving read-out accuracy of information. There is provided a semiconductor device in which an N channel type memory transistor, a selection core transistor, and a selection bulk transistor are respectively electrically coupled in series. The memory transistor and the selection core transistor are formed in a silicon layer of an SOI substrate, and the selection bulk transistor is formed in a semiconductor substrate. A word line is coupled to a memory gate electrode of the memory transistor, and a bit line is coupled to the selection bulk transistor. A write-in operation is performed while applying a counter voltage opposite in polarity to a voltage applied from the word line to the memory gate electrode to the bit line.

Abstract: To provide a magnetic element which can generate a skyrmion, and a skyrmion memory which applies the magnetic element or the like. To provide a magnetic element with a chiral magnet for generating a skyrmion, the chiral magnet is made of a magnetic material having a ?-Mn type crystal structure. Also, to provide a magnetic element with a chiral magnet for generating a skyrmion, the chiral magnet is made of a magnetic material having an Au4Al type crystal structure.