Abstract: Provided is a skyrmion memory circuit capable of circularly transferring a magnetic element skyrmion, comprising one or more current paths in a magnet having a closed-path pattern that are provided surrounding an end region including an end portion of the magnet in a plane of the magnet with the closed-path pattern, and applying current between an outer terminal connected to an outer circumferential portion of the closed-path pattern and an inner circumference electrode connected to an inner circumferential portion of the closed-path pattern, transferring the skyrmion in a direction substantially perpendicular to the direction of the applied current, and circulating the skyrmion in the magnet with the closed-path pattern.

Abstract: A semiconductor device includes a memory array having a plurality of complementary cells, each including a first memory element and a second memory element, for holding binary data depending on a difference of threshold voltage therebetween, and a control circuit for initializing the complementary cells.

Abstract: A refresh circuit is configured to perform a first refresh operation for a plurality of memory banks. The first refresh operation may be performed within a first time period determined according to a first parameter. The refresh circuit may be configured to perform a second refresh operation for a partial number of memory banks among the plurality of memory banks. The second refresh operation may be performed for the partial number of memory banks that have completed the first refresh operation. The second refresh operation may be performed within the first time period.

Abstract: A semiconductor memory, including: a plurality of data terminals for transmitting data; a plurality of buffer circuits, each being coupled to a corresponding one of the data terminals; and a control circuit receiving an access command, that controls reading data from a memory cell array or writing data to the memory cell array, and a terminal setting information issued with each access command, and controlling the buffer circuits based on the access command and the terminal setting information, wherein, when the terminal setting information indicates a first mode, all of the buffer circuits function as input buffer circuits or output buffer circuits based on the access command, and wherein, when the terminal setting information indicates a second mode, a part of the buffer circuits functions as the input buffer circuits and a remaining part of the buffer circuits functions as the output buffer circuits.

Abstract: A data storage device includes a memory die. The memory die includes a resistive random access memory (ReRAM) having a first portion and a second portion that is adjacent to the first portion. A method includes determining whether to access the second portion of the ReRAM in response to initiating a first operation targeting the first portion of the ReRAM. The method further includes initiating a second operation that senses information stored at the second portion to generate sensed information in response to determining to access the second portion. The method further includes initiating a third operation to rewrite the information at the ReRAM in response to detecting an indication of a disturb condition based on the sensed information.

Abstract: A semiconductor memory apparatus includes an effective region which is a portion of the memory region and functions as a data storage space, a residual region which is another portion of the memory region, and a capacity control circuit which restricts supply of power and signals to the residual region.

Abstract: According to one embodiment, a memory device includes a stacked body and a controller. The stacked body includes a first magnetic layer, a second magnetic layer stacked with the first magnetic layer, and a first nonmagnetic layer provided between the first magnetic layer and the second ferromagnetic layer. The second ferromagnetic layer includes a first portion and a second portion stacked with the first portion. The controller causes a current to flow in the stacked body in a programming period. The programming period includes a first and a second period. The current has a first value in the first period and a second value in the second period. The second value is less than the first value.

Abstract: A memory apparatus may include first to third pads to provide first to third voltages, respectively, to internal circuits. The first pad may receive a first external voltage, and provide the first voltage. The second and third pads may receive a second external voltage. The second pad may provide the second voltage, and the third pad may provide the third voltage.

Abstract: A non-volatile memory system includes a plurality of non-volatile memory cells, one or more control circuits that perform programming of the memory cells, a power supply line that provides a supply used to program the memory cells, and a current measurement circuit. The current measurement circuit senses an indication of current on the power supply line. The one or more control circuits determine whether the programming of the memory cells is successful based on the indication of current.

Abstract: According to one embodiment, a magnetic memory element includes a first magnetic unit, a second magnetic unit, a nonmagnetic unit, and a controller. The second magnetic unit includes a first portion and a second portion. The first portion includes a first region and a second region. The controller performs a first operation and a second operation. In the first operation, the controller changes a direction of a magnetization of the first region by causing a first current to flow through the first portion in a first current direction. The first current has a first current value. In the second operation, the controller changes a direction of a magnetization of the second region by causing a second current to flow through the first portion in a second current direction. The second current has a second current value. The second current value is less than the first current value.

Abstract: A phase change non-volatile memory device has a memory array with a plurality of memory cells arranged in rows and columns, a column decoder and a row decoder designed to select columns, and, respectively, rows of the memory array during operations of programming of corresponding memory cells. A control logic, coupled to the column decoder and the row decoder, is designed to execute a sequential programming command, to control the column decoder and row decoder to select one column of the memory array and execute sequential programming operations on a desired block of memory cells belonging to contiguous selected rows of the selected column.

Abstract: A resistive memory system having a plurality of memory cells includes a memory device having a resistive memory cell array and a controller. The controller generates write data to be written to the memory cell array by encoding input data such that the input data corresponds to an erase state and a plurality of programming states that a memory cell may have. The input data is encoded such that at least one of the number of memory cells assigned a first programming state and the number of memory cells assigned a second programming state is smaller than at least one of the numbers of memory cells in the erase state and the other programming states. The first programming state has a highest resistance level among the plurality of programming states, and the second programming state has a second highest resistance level among the plurality of programming states.

Abstract: Apparatuses and methods for providing a program voltage responsive to a voltage determination are described. An example apparatus includes a memory array comprising a plurality of access lines. The example apparatus further includes a memory access circuit coupled to the memory array. The memory access circuit is configured to, during a memory program operation, provide an inhibit voltage to the plurality of access lines. The memory access circuit is further configured to, during the memory program operation, provide a program voltage to a target access line of the plurality of access lines responsive to a determination that an access line of the plurality of access lines has a voltage equal to or greater than a threshold voltage. The threshold voltage is less than the inhibit voltage.

Abstract: A method can include storing a plurality of addresses within one cycle of a timing clock, each address corresponding to a storage location of a memory device; and following the one cycle, accessing a plurality of banks of the memory device in response to the stored addresses corresponding to different banks and preventing access to any one of the plurality of banks by more than one address of the one cycle; wherein each bank includes memory cells arranged into rows and columns that comprise the storage locations.

Abstract: A disclosed example accesses a binary value latched by a sense amplifier in circuit with a memory cell, the binary value latched by the sense amplifier in response to a counter reaching a trigger count value, the trigger count value selected from a plurality of different trigger count values based on a characteristic of the memory cell; determines a programmed state of the memory cell based on the binary value; and performs a memory operation based on the programmed state of the memory cell.

Abstract: A semiconductor memory apparatus may include a data storage region, a pipe register group, and an output driver. The data storage region may store data and output stored data as pipe input data. The pipe register group may include a plurality of pipe registers. In response to a plurality of coupling enable signals, a plurality of pipe input signals and a plurality of pipe output signals, the pipe register group may determine a number of pipe registers receiving the pipe input data and outputting pipe output data. The output driver may drive the pipe output data and transmit output data.

Abstract: A semiconductor system may include a command processor configured to decode a command to generate an active pulse and a delayed active pulse, and a bank active signal generation circuit configured to generate a bank active signal for performing an active operation for a bank accessed by an address. The bank active signal may be disabled in synchronization with the active pulse and is enabled in synchronization with the delayed active pulse.

Abstract: An integrated circuit (IC) device can include a plurality of banks, each including a plurality of memory cells, and separately accessible according to a received bank address value, each bank configured to enable accesses on different phases of an internal clock signal; and a plurality of channel groups, each channel group including a plurality of channels, each channel including its own data connections, address connections, and control input connections for accessing the banks, the channels of different groups accessing the memory banks on the different phases of the internal clock signal.

Abstract: A storage device, apparatus, and method to write and/or read data from such storage device. The storage device, comprises a channel controller and phase change memory integrated circuits (PCM ICs) arranged in sub-channels, wherein each of the sub-channels comprises several PCM ICs connected by at least one data bus line, which at least one data bus line connects to the channel controller. The channel controller is configured to write data to and/or read data from the PCM ICs according to a matrix configuration of PCM ICs, wherein: a number of columns of the matrix configuration respectively corresponds to a number of the sub-channels, the sub-channels forming a channel, and a number of rows of the matrix configuration respectively corresponds to a number of sub-banks, the sub-banks forming a bank, wherein each of the sub-banks comprises PCM ICs that belong, each, to distinct sub-channels of the sub-channels.

Abstract: A semiconductor memory device includes a block array having an m number of memory blocks in a row direction and an n number of memory blocks in a column direction (m being an integer of 2 or more and n being an integer of 1 or more), a page selection circuit configured to select a row in the block array from which a page is to be selected, and a page buffer configured to store data to be written in a page selected by the page selection circuit or data read from the page. Each of the memory blocks includes a memory cell array having a plurality of memory cells, a row selection circuit configured to select a row of the memory cell array, and a column selection circuit configured to select a column of the memory cell array.