Abstract: A method for managing a memory apparatus including a non-volatile (NV) memory element having a plurality of physical blocks includes: obtaining a first host address and first data from a first access command; obtaining a second host address and second data from a second access command; linking the first host address to a first page of the physical block and the second host address to a second page of the physical block; storing the first data and second data into the physical block; building a valid page position table and storing the valid page position table in the volatile memory; and building a global page address linking table and storing the global page address linking table in the volatile memory. The valid page position table and the global page address linking table are loaded from the volatile memory and stored to the NV memory element at predetermined time periods.

Abstract: A method includes applying a first read voltage to a word line corresponding to a first word line address in a first read request instruction. The method also includes detecting an obtained second read request instruction. The method further includes when the second word line address included in the second read request instruction is the same as the first word line address, applying a second read voltage to the word line corresponding to the first word line address after the end of the application of the first read voltage.

Abstract: Systems and methods are disclosed including a memory device and a processing device operatively coupled to the memory device. The processing device can perform operations comprising performing a set of write operations on a first block in a first plane of the memory device and on a second block in a second plane of the memory device, performing a program verification check on the first block, responsive to determining that the first block fails the program verification check, incrementing a counter value associated with the second block; responsive to the counter value satisfying a threshold criterion, performing a failure verification operation on the second block, and responsive to determining that the second block fails the failure verification operation, retiring the second block.

Abstract: In some examples, a main word line driver may include a transistor that is driven between an on state and a high resistance state by a signal based, at least in part, on a row address. In both states, the transistor may maintain a main word line in an inactive state. When in the high resistance state, the transistor may be overridden by a decoder that drives the main word line to an active state. In some examples, a main word line driver may include a transistor maintained in a high resistance state coupled in parallel with another transistor that may be driven between an on state and an off state by a signal based, at least in part, on a row address. When the other transistor is in the off state, the high resistance state transistor may be overridden by a decoder that drives a main word line to an active state.

Abstract: Technology is disclosed herein for quickly determining which erase block is bad if there is a failure in parallel erasing a set of erase blocks. The erase blocks may be tested individually in response to a fail of the parallel multi-block erase. A voltage generator ramps up the erase voltage from a steady state magnitude towards a target magnitude. The magnitude of the erase voltage is measured at a pre-determined time. If there is a defect then the erase voltage may fail to be above a threshold voltage after the ramp-up period. If the erase voltage is below the threshold voltage after the ramp-up period then the erase block may be marked as defective. If the erase voltage is above the threshold voltage after the ramp-up period then the erase block may be marked as good.

Abstract: A phase change memory element has a memory region, a first electrode and a second electrode. The memory region is arranged between the first and the second electrodes and has a bulk zone and an active zone. The memory region is made of a germanium, antimony and tellurium based alloy, wherein germanium is in a higher percentage than antimony and tellurium in the bulk zone of the memory region. The active zone is configured to switch between a first stable state associated with a first memory logic level and a second stable state associated with a second memory logic level. The active zone has, in the first stable state, a uniform, amorphous structure and, in the second stable state, a differential polycrystalline structure including a first portion, having a first stoichiometry, and a second portion, having a second stoichiometry different from the first stoichiometry.

Abstract: A memory device includes a resistor and a controller chip. The controller chip includes a first controller, a second controller, a first set of input/output (I/O) circuits, a second set of I/O circuits, a first calibration circuit, a second calibration circuit, and an arbitration circuit. The first controller transmits a first controller calibration request. The second controller transmits a second controller calibration request. The arbitration circuit instructs the first calibration circuit to perform a first controller calibration on the first set of I/O circuits using the resistor in response to the first controller calibration request, and instructs the second calibration circuit to perform a second controller calibration on the second set of I/O circuits using the resistor in response to the second controller calibration request. A first time interval of performing the first controller calibration and a second time interval of performing the second controller calibrations are non-overlapping.

Abstract: Methods, apparatus, systems and articles of manufacture are disclosed for multi-banked victim cache with dual datapath. An example cache system includes a storage element that includes banks operable to store data, ports operable to receive memory operations in parallel, wherein each of the memory operations has a respective address, and a plurality of comparators coupled such that each of the comparators is coupled to a respective port of the ports and a respective bank of the banks and is operable to determine whether a respective address of a respective memory operation received by the respective port corresponds to the data stored in the respective bank.

Abstract: A multiply accumulate circuit receives m one-bit neuron values from a first layer of a neural network system. The multiply accumulate circuit includes m non-volatile memory cells and m current sources. In addition, m current paths are defined by the m non-volatile memory cells and the m current sources collaboratively. A first current path is defined by a first non-volatile memory cell and a first current source. A first terminal of the first current source receives a first supply voltage. A second terminal of the first current source is connected with a first terminal of the first non-volatile memory cell. A second terminal of the first non-volatile memory cell is connected with an output terminal of the multiply accumulate circuit. A control terminal of the first current source receives a first one-bit neuron value.

Abstract: Provided is a semiconductor apparatus including a power supply pin configured to receive a power supply voltage from an outside, a capacitor connection pin to be connected with a capacitor, a power supply circuit having an input connected to the power supply pin and having an output connected to the capacitor connection pin, the power supply circuit being configured to generate an internal power supply voltage at the output of the power supply circuit, a nonvolatile memory configured to operate by receiving the internal power supply voltage, a switch disposed between a power supply terminal of the nonvolatile memory and the capacitor connection pin, and, a control unit configured to turn on the switch when the internal power supply voltage exceeds a predetermined threshold value.

Abstract: A neuromorphic device includes a memory cell array including first resistive memory cells connected to word lines, bit lines and source lines, second resistive memory cells connected to the word lines, at least one redundancy bit line and at least one redundancy source line, third resistive memory cells connected to at least one redundancy word line, the bit lines and the source lines. The memory cell array stores data corresponding to a weight of a neural network in the first resistive memory cells, and is configured to generate a plurality of read currents based on input signals and the data. The neuromorphic device further includes an analog to digital converter (ADC) circuit configured to convert the plurality of read currents into a plurality of digital signals.

Abstract: A superconducting distributed bidirectional current driver system includes multiple bidirectional current drivers, a bidirectional current load being operatively coupled between two adjacent bidirectional current drivers. Each of the bidirectional current drivers includes first and second superconducting latch circuits. The first superconducting latch circuit in a first one of the bidirectional current drivers and the second superconducting latch circuit in a second one of the bidirectional current drivers coupled to the current load are selectively activated by first and second activation signals, respectively, to establish a first current path through the current load in a first direction.

Abstract: The present disclosure belongs to the technical field of information storage, and particularly relates to a method for information storage based on a hybrid material. The method for information storage based on a hybrid material provided by the present disclosure includes a step of applying an external force to a hybrid material for driving, such that the hybrid material shows a fluorescent state or a non-fluorescent state, thereby realizing two-state or three-state information storage. By only applying the external force to the selected hybrid material for driving, energy band alignment methods can be transformed under the driving of the external force with an energy level difference between different components in the hybrid material. Therefore, the hybrid material shows the component fluorescent state or the non-fluorescent state. One storage cell has two or three states, so the present disclosure can be used to store two-state or three-state data.

Abstract: A memory device that includes a first memory cell, a second memory cell and a sense amplifier. The sense amplifier includes a first branch and a second branch and are configured to output a first voltage and a second voltage to the first memory and the second memory, respectively in a trimming operation. A first clamp device of the sense amplifier includes a first clamp transistor and a plurality of first trimming transistors that are coupled to the first clamp transistor in parallel. The gate terminals of the first clamp transistor and the plurality of first trimming transistors are biased by a fixed clamp voltage. Each of the plurality of first trimming transistors is selectively conducted to compensate a mismatch between the first voltage and the second voltage.

Abstract: Described is a low power, high-density non-volatile differential memory bit-cell. The transistors of the differential memory bit-cell can be planar or non-planer and can be fabricated in the frontend or backend of a die. A bit-cell of the non-volatile differential memory bit-cell comprises first transistor first non-volatile structure that are controlled to store data of a first value. Another bit-cell of the non-volatile differential memory bit-cell comprises second transistor and second non-volatile structure that are controlled to store data of a second value, wherein the first value is an inverse of the second value. The first and second volatile structures comprise ferroelectric material (e.g., perovskite, hexagonal ferroelectric, improper ferroelectric).

Abstract: A magnetoresistive random access memory (MRAM) array includes MRAM cells, each MRAM cell having a corresponding Magnetic Tunnel Junction (MTJ) capable of being in a blown state or non-blown state, in which the blown state corresponds to a permanent breakdown of a tunnel dielectric layer of the corresponding MTJ. Write circuitry performs a one-time-programmable (OTP) write operation to blow selected MRAM cells. For each MRAM cell being blown, the write circuitry uses an initial OTP program reference for the MRAM cell being blown to detect onset of tunnel dielectric breakdown after application of each OTP write pulse of the OTP write operation. After detection of the onset, the write circuitry updates the initial OTP program reference, applies at least one additional OTP write pulse to the MRAM cell being blown, and uses the updated OTP program reference to verify that current saturation of the MRAM cell being blown has occurred.

Abstract: Numerous embodiments of analog neural memory systems that enable concurrent write and verify operations are disclosed. In some embodiments, concurrent operations occur among different banks of memory. In other embodiments, concurrent operations occur among different blocks of memory, where each block comprises two or more banks of memory. The embodiments substantially reduce the timing overhead for weight writing and verifying operations in analog neural memory systems.

Abstract: Systems, devices, methods, and circuits for managing reference currents in semiconductor devices. In one aspect, a semiconductor device includes: a memory cell array configured to store data in sets of memory cells and circuitry coupled to the memory cell array. Each set of one or more sets of memory cells in the memory cell array is associated with a respective reference current, and memory cells in sets associated with different reference currents have different threshold voltage distributions. The circuitry is configured to: determine information associated with a reference current for a set of memory cells in the memory cell array based on a memory address corresponding to the set, generate the reference current based on the information associated with the reference current for the set, and sense one or more memory cells in the set based on the reference current.

Abstract: Disclosed in the present invention are a highly energy-efficient CAM based on a single FeFET and an operating method thereof, which relate to a design of an FeFET-based memory suitable for low power consumption and high performance. A brand-new design of a CAM cell based on the single FeFET is achieved by fully utilizing the storage characteristics of the FeFET, so that the number of transistors is saved, the search energy consumption is reduced, and the nonvolatility of data storage is obtained. The present invention utilizes a 2T-1FeFET structure, and combines the advantages of the FeFET and CMOS. Without reducing performance, only one FeFET is utilized to implement a less area overhead and a lower energy consumption compared with a traditional CMOS-based CAM, and non-volatility is achieved.

Abstract: The present disclosure relates to systems and methods implemented on a memory controller for detecting and mitigating memory attacks (e.g., row hammer attacks). For example, a memory controller may track activations of row addresses within a memory hardware (e.g., a DRAM device) and determine whether a pattern of activations is indicative of a row hammer attack. This is determined using a counting mode for corresponding memory sub-banks. Where a likely row hammer attack is detected, the memory controller may activate a sampling mode (rather than the counting mode) for a particular sub-bank to identify which of the row addresses should be refreshed on the memory hardware. The implementations described herein provide a low computational cost alternative to heavy-handed detection mechanisms that require access to significant computing resources to accurately detect and mitigate row hammer attacks.