Patents Examined by Jay W. Radke
  • Patent number: 11177000
    Abstract: An operating method of a non-volatile memory includes: generating a first programming pulse with a first time period to a target memory cell in a memory array; reading and verifying whether a threshold voltage of the target memory cell reaches a target voltage level; and generating a second programming pulse with a second time period to the target memory cell when the threshold voltage of the target memory cell does not reach the target voltage level, wherein the second time period is longer than the first time period.
    Type: Grant
    Filed: June 19, 2019
    Date of Patent: November 16, 2021
    Assignee: MACRONIX INTERNATIONAL CO., LTD.
    Inventors: Guan-Wei Wu, Yao-Wen Chang, Chih-Chieh Cheng, I-Chen Yang
  • Patent number: 11177002
    Abstract: A storage device including control circuitry, communicatively coupled to a non-volatile memory, configured to receive a parity bit that has been stored using a data structure, and to receive a first subset of host data that includes block data relating to a set of memory cells. The control circuitry may be configured to perform a read operation to identify a second subset of host data that includes additional block data relating to the set of memory cells. The control circuitry may be configured to decode the second subset of host data using the parity bit. The control circuitry may be configured to perform a write operation to write the block data to at least one or more memory cells that are part of the set of memory cells.
    Type: Grant
    Filed: June 30, 2020
    Date of Patent: November 16, 2021
    Assignee: SanDisk Technologies LLC
    Inventors: Xue Pitner, Ravi Kumar, Deepanshu Dutta
  • Patent number: 11176974
    Abstract: In some examples, a memory device may have at least a first and a second memory array. In some cases, a portion of the bit cells of the first memory array may be coupled to first PMOS-follower circuitry and to second PMOS-follower circuitry. A portions of the bit cells of the second memory array may also be coupled to the second PMOS-follower circuitry and to third PMOS-follower circuitry. Additionally, in some cases, the portion of bit cells of both the first memory array and the second memory array may be coupled to shared preamplifier circuitry.
    Type: Grant
    Filed: July 22, 2019
    Date of Patent: November 16, 2021
    Assignee: Everspin Technologies Inc.
    Inventors: Syed M. Alam, Thomas S. Andre
  • Patent number: 11169732
    Abstract: According to one embodiment, a computing device includes a first magnetic section, a first reading section, a memory section, and a computing section. The first reading section is configured to output a first signal corresponding to a magnetization state of a partial region of the first magnetic section. The computing section is configured to perform computation using the first signal when first information stored in the memory section is in a first state, and to perform computation using a reverse signal of the first signal when the first information is in a second state.
    Type: Grant
    Filed: March 19, 2018
    Date of Patent: November 9, 2021
    Assignee: KABUSHIKI KAISHA TOSHIBA
    Inventors: Rie Sato, Koichi Mizushima, Hayato Goto
  • Patent number: 11170845
    Abstract: Certain aspects of the present disclosure are directed to a memory system. The memory system generally includes a word line (WL) driver circuit comprising a transistor coupled between a WL of a memory and a reference potential node. The memory system also includes a clamping circuit having logic configured to generate a control signal to drive a gate of the transistor such that the control signal is floating when the first head switch is open, and a first head switch coupled between a voltage rail and a supply input of the logic.
    Type: Grant
    Filed: July 14, 2020
    Date of Patent: November 9, 2021
    Assignee: Qualcomm Incorporated
    Inventors: Arun Babu Pallerla, Derek Yang, Chulmin Jung, Changho Jung
  • Patent number: 11164639
    Abstract: According to one embodiment, a semiconductor memory device includes: a memory cell array; a conversion circuit; a data bus; a first buffer and a second buffer; and a third buffer. The data bus includes a first wiring part extending along a first direction. The first buffer and the second buffer are separate from each other. The first to third buffers are at different positions along the first direction.
    Type: Grant
    Filed: September 5, 2019
    Date of Patent: November 2, 2021
    Assignee: TOSHIBA MEMORY CORPORATION
    Inventors: Hiromi Noro, Yusuke Ochi, Takahiro Sugimoto, Naoaki Kanagawa
  • Patent number: 11164033
    Abstract: A processor-in-memory device includes a memory array, a sense amplifier, and a processing unit that has an accumulator. The processing unit is configured to receive a set of data. The processing unit then uses the sense amplifier and the accumulator to generate a first histogram of the set of data.
    Type: Grant
    Filed: May 27, 2016
    Date of Patent: November 2, 2021
    Assignee: Micron Technology, Inc.
    Inventor: Jeremiah James Willcock
  • Patent number: 11152061
    Abstract: A system and method of storing and reading digital data, including providing a nanopore polymer memory (NPM) device having at least one memory cell comprising at least two addition chambers each arranged to add a unique chemical construct (or codes) to a polymer (or DNA) string when the polymer enters the respective addition chamber, the data comprising a series of codes; successively steering the polymer from deblock chambers through the nanopore into the addition chambers to add codes to the polymer to create the digital data pattern on the polymer; and accurately controlling the bit rate of the polymer using a servo controller. The device may have loading chamber(s) to load (or remove) the polymer into/from the deblock chambers through at least one “micro-hole”. The cell may be part of a memory system that stores and retrieves “raw” data and allows for remote retrieval and conversion. The cell may store multi-bit data having a plurality of states for the codes.
    Type: Grant
    Filed: May 4, 2020
    Date of Patent: October 19, 2021
    Assignee: IRIDIA, INC.
    Inventors: Paul F. Predki, John Stuart Foster
  • Patent number: 11145382
    Abstract: A leakage measuring circuit includes a bias input node control circuit and provides a signal indicative of a leakage current through the bias input node. The bias input node control circuit includes a first input to receive an indication of a reference voltage, a second input to receive an indication of a voltage of the bias input node, and an output to bias the bias input node at the reference voltage based on a relationship between the first and second input. A well voltage bias circuit provides a well bias voltage and includes a well bias control circuit including a first input to receive the signal indicative of the leakage current, a second input to receive a signal indicative of a reference leakage current value, and an output for controlling the well bias voltage based on a relationship between the first and second input of the well bias control circuit.
    Type: Grant
    Filed: May 11, 2020
    Date of Patent: October 12, 2021
    Assignee: NXP USA, Inc.
    Inventors: Karthik Ramanan, Jon Scott Choy, Jacob T. Williams
  • Patent number: 11145339
    Abstract: A computing device and method are provided. The computing device in some examples includes multiple digital-to-analog converters (DACs) having outputs connected to respective operational amplifiers, with outputs connected to the gates of respective transistors, each forming a serial combination with a respective memory element. The serial combinations are connected between a voltage reference point and a conductive line. An analog-to-digital converter is connected to the conductive line at the input. The DACs generate analog signals having ON-period lengths corresponding to the respective numbers at the DACs' inputs. The transistors generate currents indicative of the levels of output signals of the respective DACs and memory states of the respective memory elements for the ON-periods. The combined currents charge or discharge the conductive line to a voltage indicative of the sum of the numbers weighted by the memory states. The voltage is converted to a digital representation of the weighted sum.
    Type: Grant
    Filed: May 22, 2020
    Date of Patent: October 12, 2021
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
    Inventors: Jaw-Juinn Horng, Chin-Ho Chang, Yung-Chow Peng
  • Patent number: 11145354
    Abstract: An exemplary semiconductor device includes a clock generator circuit configured to generate a clock signal, and a duty cycle adjustment circuit configured to receive the clock signal. The duty cycle adjustment circuit includes an adjuster circuit configured to receive a back-bias voltage and to adjust a duty cycle of the clock signal based on the back-bias voltage to provide an output dock signal.
    Type: Grant
    Filed: March 11, 2021
    Date of Patent: October 12, 2021
    Assignee: Micron Technology, Inc.
    Inventors: Michael V. Ho, Myung Ho Bae
  • Patent number: 11134788
    Abstract: Methods and devices for reading a memory cell using multi-stage memory sensing are described. The memory cell may be coupled to a digit line after the digit line during a read operation. A transistor may be activated to couple an amplifier capacitor with the digit line during the read operation. The transistor may be deactivated for a portion of the read operation to isolate the amplifier capacitor from the digit line while the memory cell is coupled to the digit line. The transistor may be reactivated to recouple the amplifier capacitor to the digit line to help determine the value of the memory cell.
    Type: Grant
    Filed: February 2, 2021
    Date of Patent: October 5, 2021
    Assignee: Micron Technology, Inc.
    Inventors: Huy T. Vo, Adam S. El-Mansouri
  • Patent number: 11127463
    Abstract: Discussed herein are systems and methods for charging an access line to a non-volatile memory cell during a standby state, such as to prevent or mitigate standby-state charge loss. An embodiment of a memory device comprises a memory cell, a string driver circuit, and a charging circuit. The string driver circuit is coupled to the memory cell via a local word line, and has a common p-well. The charging circuit, in response to a voltage of a global word line of the memory device falling below a reference voltage during a standby state, couple a supply voltage to the common p-well of the string driver circuit to charge the global word line to a positive bias potential. The memory device includes a leakage compensation circuit to compensate for the junction leakage.
    Type: Grant
    Filed: February 3, 2021
    Date of Patent: September 21, 2021
    Assignee: Micron Technology, Inc.
    Inventor: Shigekazu Yamada
  • Patent number: 11114166
    Abstract: According to one embodiment, a semiconductor memory device includes a bit line electrically connected to a memory cell, a first node electrically connected to the bit line, a first driver configured to increase a voltage of the first node to a first voltage, a first buffer circuit configured to store data based on the voltage of the first node, a bus electrically connected to the first buffer circuit, a first transistor electrically connected between the first node and the bus, and a second buffer circuit electrically connected to the bus. The first buffer circuit is electrically connected to an input terminal of the first driver. The first driver changes a voltage of the bus based on the data stored in the first buffer circuit.
    Type: Grant
    Filed: September 5, 2019
    Date of Patent: September 7, 2021
    Assignee: TOSHIBA MEMORY CORPORATION
    Inventors: Atsushi Okuyama, Yoshihiko Kamata, Hiromitsu Komai, Takuyo Kodama, Yuki Ishizaki, Yoko Deguchi, Hiroyuki Kaga
  • Patent number: 11107510
    Abstract: Apparatuses and methods related to memory bank power coordination in a memory device are disclosed. A method for memory bank power coordination may include concurrently performing a memory operation by a threshold number of memory regions, such as banks or subarrays, and executing a command to cause a budget area, such as a register, to perform a power budget operation associated with the memory operation. The threshold number of memory regions may be set based at least in part on a threshold power consumption value, and the number of memory regions to concurrently perform an operation may be controlled by a bank arbiter. A counter having a value representing the threshold number of memory regions may be decremented while performing an operation or incremented upon completion of an operation associated with one of the memory regions. A number of the memory regions may be selected to perform a processing-in-memory operation.
    Type: Grant
    Filed: October 18, 2019
    Date of Patent: August 31, 2021
    Assignee: Micron Technology, Inc.
    Inventors: Kelley D. Dobelstein, Jason T. Zawodny, Kyle B. Wheeler
  • Patent number: 11100977
    Abstract: Systems and methods of dynamically calibrating memory control signals during increase of wordline voltage for memory technologies subject to charge loss are disclosed. In one aspect, an exemplary method may comprise using an internal node, such as a wordline regulator output or return feedback line or a replica of the wordline, as proxy for the local wordline voltage. In one or more further embodiments, the proxy signal may be converted to digital signal or code and even determined in the background before the signal is needed for calibration. As a function of the disclosed technology, calibration of memory control signals, such as pass voltage and wordline read-verify voltage, may be performed during increase of the wordlines voltage with no impact or penalty on read/program time.
    Type: Grant
    Filed: November 13, 2020
    Date of Patent: August 24, 2021
    Assignee: Micron Technology, Inc.
    Inventor: Michele Piccardi
  • Patent number: 11101001
    Abstract: A non-volatile memory system includes a control circuit connected to non-volatile memory cells. The control circuit is configured to simultaneously program memory cells connected to different word lines that are in different sub-blocks of different blocks in different planes of a die.
    Type: Grant
    Filed: June 28, 2018
    Date of Patent: August 24, 2021
    Assignee: SANDISK TECHNOLOGIES LLC
    Inventors: Henry Chin, Zhenming Zhou
  • Patent number: 11094365
    Abstract: An information handling system includes a memory array and a memory controller. The memory array stores data within the information handling system. The memory controller writes the data to the memory array. The memory controller also determines whether a temperature of the memory array is above a threshold temperature. The memory controller tags a plurality of memory locations within the memory array written with data while the temperature is above the threshold temperature. While a refresh operation is being executed, the memory controller determines whether the temperature of the memory array is below the threshold temperature. In response to the temperature of the memory array being below the threshold temperature and while the refresh operation is being executed, the memory controller rewrites the data in the tagged memory locations within the memory array.
    Type: Grant
    Filed: March 17, 2020
    Date of Patent: August 17, 2021
    Assignee: Dell Products L.P.
    Inventors: Young Hwan Jang, Lip Vui Kan
  • Patent number: 11087814
    Abstract: The present disclosure relates to a structure including a non-fixed read-cell circuit configured to switch from a first state to a second state based on a state of a memory cell to generate a sensing margin.
    Type: Grant
    Filed: July 11, 2019
    Date of Patent: August 10, 2021
    Assignee: GLOBALFOUNDRIES U.S. INC.
    Inventors: Amogh Agrawal, Ajey Poovannummoottil Jacob, Bipul C. Paul
  • Patent number: 11086546
    Abstract: Systems, methods, and software are disclosed herein that enhance data storage operations. In various implementations, a preserve write process identifies one or more regions of the solid-state memory components that qualify to be relocated prior to a data storage device entering a data retention state. Prior to the data retention state, the process changes one or more values, of one or more write settings, to one or more new values. With the write settings changed to the one or more new values, the process relocates data from the one or more regions to one or more new regions. After having relocated the data, the process returns the one or more new values, of the one or more write settings, to one or more earlier values.
    Type: Grant
    Filed: January 17, 2020
    Date of Patent: August 10, 2021
    Assignee: Microsoft Technology Licensing, LLC
    Inventors: Vamsi Sata, Dillip Kumar Dash