Abstract: A nonvolatile memory device including a memory cell array including a plurality of nonvolatile memory cells and a row decoder connected with the memory cell array through wordlines may be provided. The row decoder may be configured to precharge a first wordline corresponding to a first row address from among the wordlines, in response to receiving the first row address together with a first command, and maintain a precharge state of the first wordline, in response to receiving a second row address being identical to the first row address together with a second command following the first command.

Abstract: A semiconductor device capable of monitoring a connection state of a terminal on a semiconductor chip includes a selector configured to acquire terminal levels of a plurality of respective terminals on the semiconductor chip to which an inspection pattern is inputted based on a detection signal, a memory configured to store latch data based on a chip address which identifies the semiconductor chip and a plurality of the terminal levels corresponding to the plurality of terminals based on the detection signal, an output circuit configured to read a plurality of pieces of latch data from the memory based on the detection signal and to output the plurality of pieces of latch data, and a timing control circuit configured to generate the detection signal by detecting an edge of a clock inputted during an inspection mode and configured to activate the selector, the memory, and the output circuit.

Abstract: Methods, systems, and devices for system and method for reading and writing memory management data through a non-volatile cell based register are described. A memory device may include a set of latch units addressable via a set of row lines and a set of column lines. Each latch unit may include a sense amplifier coupled with a first line and a first non-volatile capacitor coupled with the first line and a second line, where the first capacitor is configured to store a charge representing one or more bits. Additionally, each latch unit may include a second capacitor coupled with the first line and a third line, where the second capacitor is configured to amplify a voltage at the first line based on the charge stored in the first capacitor.

Abstract: A system can include a memory device and a processing device to perform operations that include determining a calibration scan frequency based on an amount of elapsed time since a previous write operation performed on the memory device, determining, based on the calibration scan frequency, whether one or more scan criteria are satisfied, responsive to determining that the one or more scan criteria are satisfied, identifying one or more block families, and calibrating one or more bin pointers of each of the identified block families, wherein the calibrating comprises: for each of the identified block families, updating each of the one or more bin pointers of the identified block family based on a data state metric of at least one block of the identified block family.

Abstract: Storage devices are capable of utilizing failed bit count (FBC) reduction devices to reduce FBCs for word lines in blocks. An FBC reduction device may include a FBC count component, a threshold component, a pre-verify component, and a soft program component. The FBC count component may access the FBC for the word line, where the block has unprogrammed word lines in an unprogrammed region separated from programmed word lines of a programmed region by the word line. The threshold component may determine whether the FBC of the word line exceeds a predetermined threshold. When the FBC exceeds the threshold, the pre-verify component may perform pre-verify operations on the programmed region. The soft program component may program the word line with first data equal to second data programmed in a second block. In response to disabling pre-verify operations, the program component may program the unprogrammed word lines in the unprogrammed region.

Abstract: There are provided a memory device and an operating method thereof. The memory device includes: a memory block including a plurality of memory cells; and a peripheral circuit for performing a program operation and an erase operation on the memory block. The program operation is performed by using a hole injection method, and the erase operation is performed by using an electron charging method. The plurality of memory cells are programmed when a threshold voltage of each of at least some of the plurality of memory cells is decreased to be less than a set level in the program operation, and are erased when the threshold voltage of each of the plurality of memory cells is increased to be the set level or higher in the erase operation.

Abstract: Technology is disclosed herein for testing circuitry that controls memory operations in a memory structure having non-volatile memory cells. The testing of the circuitry can be performed without the memory structure. The memory structure may reside on one semiconductor die, with sense blocks and a control circuit on another semiconductor die. The control circuit is able to perform die level control of memory operations in the memory structure. The control circuit may control the sense blocks to simulate sensing of non-volatile memory cells in the memory structure even though the sense blocks are not connected to the memory structure. The control circuit verifies correct operation of the semiconductor die based on the simulated sensing. For example, the control circuit may verify correct operation of a state machine that controls sense operations at a die level. Thus, the operation of the semiconductor die may be tested without the memory structure.

Abstract: A nonvolatile memory device includes a plurality of memory blocks and a control logic circuit configured to perform a first page on-chip valley search (OVS) operation on memory cells connected to one wordline of a memory block selected in response to an address, among the plurality of memory blocks, in response to a first read command. The control logic circuit is further configured to change a read level of at least one state using detection information of the first page OVS operation, and to perform a second page read operation on the memory cells using the changed read level in response to a second read command.

Abstract: Apparatuses and methods can be related to implementing a Bayesian neural network in a memory. A Bayesian neural network can be implemented utilizing a resistive memory array. The memory array can comprise programmable memory cells that can be programed and used to store weights of the Bayesian neural network and perform operations consistent with the Bayesian neural network.

Abstract: A processing device of a memory sub-system is configured to detect a power on event that is associated with a memory device and indicates that power has been restored to the memory device; estimate a duration of a power off state preceding the power on event associated with the memory device; and update voltage bin assignments of a plurality of blocks associated with the memory device based on the duration of the power off state.

Abstract: Methods of peak power management (PPM) for a storage system having multiple memory dies are disclosed. Each memory die includes a first PPM circuit and a second PPM circuit. First PPM circuits of the multiple memory dies are electrically connected to form a first PPM group. Similarly, second PPM circuits are electrically connected to form a second PPM group. Peak power operations can be managed by switching on a first pull-down driver of the first PPM circuit on a selected memory die when a first PPM enablement signal of the first PPM group is zero; waiting for a first delay period; switching on a second pull-down driver of the second PPM circuit on the selected memory die when a second PPM enablement signal of the second PPM group is zero. The first and second PPM enablement signals depend on the current flowing through each pull-down driver in the first and second PPM groups.

Abstract: A non-volatile memory device includes a memory cell array including memory cells, a page buffer circuit including page buffers respectively connected to bit lines, a buffer memory, and a control logic configured to control a read operation on the memory cells. In the read operation, the control logic obtains valley search detection information including read target block information and word line information by performing a valley search sensing operation on a distribution of threshold voltages of the memory cells, obtains a plurality of read levels using a read information model by inputting the valley search detection information into the read information model, and performs a main sensing operation for the read operation.

Abstract: A system includes a memory device having a plurality of dice and A processing device to perform operations, including determining a representative number of program-erase cycles performed across the plurality of dice. The operations further include tracking the representative number of program-erase cycles over time. The operations further include, in response to the representative number of program-erase cycles satisfying a first threshold criterion, adding an additional threshold voltage offset bin to a plurality of threshold voltage offset bins for the memory device, wherein each of the plurality of threshold voltage offset bins comprises a corresponding window of time after program of data to the memory device.

Abstract: Some embodiments include apparatuses and methods of operating the apparatuses. One of the apparatuses includes a first memory block including first word lines for respective first memory cells of the first memory block; a second memory block including second word lines for respective second memory cells of the second memory block; first diffusion regions coupled to the first word lines; second diffusion regions adjacent the first diffusion regions, the second diffusion regions coupled to the second word lines; and a circuit to apply a voltage to the second diffusion regions in a write operation performed on the first memory block.

Abstract: A memory device comprising: a plurality of memory blocks each including a plurality of word lines arranged between a first and second select line, a peripheral circuit performs an erase operation by applying an erase voltage to a source or drain line of a selected memory block, and a control logic controls, in a period in which the erase operation is performed, the peripheral circuit to: sequentially select the plurality of word lines included in the selected memory block at least one by one from a word line closest to the first and second select line to a word line farthest from the first and second select line, apply a first erase permission voltage to the selected word lines, and apply a second erase permission voltage, which have a higher potential level than the first erase permission voltage, to remaining word lines except the selected word lines.

Abstract: Control logic in a memory device initiates an erase operation on a memory array and causes an erase voltage signal to be applied to a source terminal of a string of memory cells in a data block of the memory array during the erase operation. The control logic further causes a first voltage signal to be applied to a first select line of the data block and a second voltage signal to be applied to a second select line of the data block, wherein the first select line is coupled to a first device in the string of memory cells and the second select line is coupled to a second device in the string of memory cells, and wherein the first voltage signal and the second voltage signal both have a common first voltage offset with respect to the erase voltage signal during a first stage of the erase operation.

Abstract: An electronic device includes a memory device receiving a power supply voltage, a data strobe signal, and a data signal, and a system-on-chip that exchanges data with the memory device using the data strobe signal and the data signal. The system-on-chip performs write training that measures a magnitude of a delay of the data strobe signal due to variation in the level of the power supply voltage and adjusts a delay of the data signal using a result of the write training.

Abstract: The present technology relates to a semiconductor memory device and a method of operating the same. The semiconductor memory device includes a memory cell array including a plurality of memory blocks, a peripheral circuit configured to perform a program operation on a selected memory block among the plurality of memory blocks, and control logic configured to control the peripheral circuits to perform a retention acceleration operation including boosting a channel of a plurality of cell strings included in the selected memory block between a program voltage applying operation and a program verify operation during the program operation.

Abstract: A semiconductor device includes a first transistor; a first resistor; a second resistor; a first circuit configured to apply a first voltage to the first transistor. The first voltage is based on a difference between a reference voltage and an output voltage divided by the first and second resistors. A first current through the first circuit in a first mode is less than a second current through the first circuit in a second mode. The semiconductor device includes a capacitor connected to the output terminal; and a second circuit connected to the capacitor that: (a) disconnects the first circuit from the capacitor and apply a second voltage to the capacitor in a first mode, and (b) electrically connects the first circuit to the capacitor in the second mode.

Abstract: The present disclosure describes embodiments of a write assist circuit. The write assist circuit can include a boost circuit configured to output a first negative voltage at a first output terminal, and an adjustment circuit configured to couple the first negative voltage to a second negative voltage higher than the first negative voltage. The adjustment circuit can include a transistor, and a second output terminal electrically connected to the first output terminal. The transistor can include a first source/drain terminal, a second source/drain terminal, and a gate terminal. The first source/drain terminal can be electrically coupled to the second output terminal. The second source/drain terminal can be electrically connected to a voltage source. The gate terminal can be electrically connected to a ground voltage supply.