Abstract: This application relates to a data transmission circuit, a method making it, and a storage device. The circuit includes a mode register data storage unit and an array area data storage unit. The mode register data storage unit outputs mode register data in response to a first clock signal; the output terminal of the array area data storage unit and the output terminal of the mode register data storage unit are both connected to the first node, the array area data storage unit receives array area data in response to the first pointer signal, and outputs the array area data in response to the second pointer signal. This technic can accurately control the mode register data and the array area data to output through the respective output channels in turn.

Abstract: An electronic device includes multiple memory elements including multiple redundant memory elements. The electronic device also includes repair circuitry configured to remap data to the multiple memory elements when a failure occurs. The repair circuitry includes multiple fuse latches configured to implement the remapping. The repair circuitry also includes latch testing circuitry configured to test functionality of the multiple fuse latches. The latch testing circuitry includes selection circuitry configured to enable selection of a first set of fuse latches of the multiple fuse latches for a test separate from a second set of fuse latches of the multiple fuse latches that are unselected by the selection circuitry.

Abstract: Systems and methods described herein may enable a memory system to selectively provide a signal boost to a memory cell in response to a change in operating condition, like a change in temperature. The systems and methods may include determining to generate a signal boost for a first duration of time and in response to determining to generate the signal boost, generating the signal boost causing an increase in voltage applied to a signal line coupled to a memory cell. The systems and methods may further include, after the first duration of time, ceasing generation of the signal boost.

Abstract: A superconducting memory circuit for applying and propagating superconducting signals through a plurality of superconducting wires in the memory circuit is provided. The memory circuit includes multiple passive cells arranged in a plurality of sets. Each set of passive cells has associated therewith at least one common superconducting wire interconnecting a subset of the passive cells in the set of passive cells. The memory circuit further including at least one power-signal propagation circuit, an input of the power-signal propagation circuit being coupled with a preceding set of passive cells via a first superconducting wire, and an output of the power-signal propagation circuit being coupled with a subsequent set of passive cells via a second superconducting wire. Upon application of a first superconducting signal to the first superconducting wire, the power-signal propagation circuit applies a second superconducting signal to the second superconducting wire.

Abstract: In some examples, command decoders may have multiple command paths. In some examples, command signals from one command path may be provided to another command path from a node located between two latches of the command decoder, such as two latches of a flip-flop. In some examples, the command decoder may include separate flip-flops for different command modes. In some examples, the separate flip-flops may be tristate flip-flops. In some examples, the command decoder may include alternate logic circuits rather than a multiplexer.

Abstract: Exemplary methods, apparatuses, and systems include an environmental operations manager for controlling memory access of the memory device. The environmental operations manager receives a set of data bits for programming to a memory location. The environmental operations manager receives environmental condition data. The environmental operations manager delays programming of the set of data bits to the memory location and writing the set of data bits to a buffer location in response to determining that the environmental condition data satisfies a threshold.

Abstract: A command/address sequence associated with a read/write operation for a memory device utilizes various existing command/address clock signals in a novel way that obviates the need to utilize the I/O bus. As such, the command/address sequence can be performed in parallel with the DIN/DOUT operations, thereby removing the performance bottleneck that would otherwise be caused by the command and address sequencing. The command/address sequence encodes bit information on first and second enable signals and utilizes rising or falling edges of a clock signal to latch the encoded bit information, which can then be decoded to determine corresponding command and address codes. A chip select sequence is also disclosed that enables a memory chip configuration to be employed in which each chip in a package shares a common connection to a controller but does not require hard-coded pins for performing chip select.

Abstract: A semiconductor memory device includes a first cell string, a second cell string, a peripheral circuit, and a control logic. The first cell string includes first and second drain select transistors. The second cell string includes third and fourth drain select transistors. The peripheral circuit performs a program operation on the fourth drain select transistor included in the second cell string. The threshold voltage of the first drain select transistor is set through an ion implantation process. The threshold voltage of the fourth drain select transistor is set through the program operation.

Abstract: Systems, apparatus, and methods related to configurable data protection circuitry. A memory includes a plurality of memory devices and a memory controller that can be coupled to the memory via a plurality of channels. The channels comprise respective subsets of the plurality of memory devices. The memory controller comprises data protection circuitry to accommodate a first codeword configuration of a number of codewords responsive to the plurality of memory devices having a first operating mode corresponding to a first input/output (I/O) width and accommodate a second codeword configuration of the number of codewords responsive to the plurality of memory devices having a second operating mode corresponding to a second I/O width, as well as switch between the first operating mode of the plurality of memory devices and the second operating mode of the plurality of memory devices.

Abstract: A semiconductor device includes: a drift detection circuit that retrieves a previously-determined first delay amount of a reference signal passing through a circuit element at a first timing, determines a second delay amount of the reference signal passing through the circuit element at a second timing, and outputs a drift amount that is a difference between the first and second delay amounts; and a delay amount adjustment circuit that retrieves a previously-determined third delay amount of a first signal transmitted to an external device at the first timing, determines a fourth delay amount based on the third delay amount and the drift amount as a delay amount to be applied to the first signal in a period after the second timing, and transmits the first signal to which the fourth delay amount has been applied, to the external device.

Abstract: A determination is made that a memory device of a memory sub-system is to be transitioned to a sleep mode. A command is initiated to cause a standby circuit associated with the memory device to enter into a low power mode while a power supply of the memory sub-system is maintained in a powered state. In the low power mode, a reference voltage is supplied to a voltage regulator of the standby circuit to supply a standby current level to the memory device during the sleep mode.

Abstract: A method for managing a memory apparatus including a plurality of physical blocks, and a volatile memory includes: obtaining a first host address and first data, and obtaining a second host address and second data; linking the first host address and second host address to a first page and second page of the physical block, and storing the first data and second data into the physical block; building a valid/invalid page count table according to a valid/invalid page count of the physical block; building a valid page position table according to the valid/invalid page count table, and storing the valid/invalid page count table in the volatile memory; and when a valid/invalid page count of the physical block indicates the physical block should be erased, using the valid page position table to move valid pages of the physical block to another physical block.

Abstract: A non-volatile memory device includes a set of memory cells, a cycle transistor, a reference transistor and a control circuit. The control circuit is coupled to the set of memory cells, the cycle transistor and the reference transistor. A method of controlling the non-volatile memory device includes in a program operation or an erase operation of the set of memory cells, the control circuit determining a state of the cycle transistor, and upon determining the cycle transistor being in an erased state (or a programmed state), the control circuit setting the reference transistor from a reference state to the erased state (or the programmed state), and then restoring the reference transistor from the erased state (or the programmed state) to the reference state. The reference state is set between the erased state and a programmed state.

Abstract: A memory unit includes at least one memory cell and a computational cell. The at least one memory cell stores a weight. The at least one memory cell is controlled by a first word line and includes a local bit line transmitting the weight. The computational cell is connected to the at least one memory cell and receiving the weight via the local bit line. Each of an input bit line and an input bit line bar transmits a multi-bit input value. The computational cell is controlled by a second word line and an enable signal to generate a multi-bit output value on each of an output bit line and an output bit line bar according to the multi-bit input value multiplied by the weight. The computational cell is controlled by a first switching signal and a second switching signal for charge sharing.

Abstract: A memory device includes a cell group and a control circuit. The cell group includes plural non-volatile memory cells, each capable of storing multi-bit data corresponding to plural program states and an erased state. The control circuit performs at least two partial program operations for programming the multi-bit data in at least two non-volatile memory cells. The at least two partial program operations include an ISPP operation to increase a threshold voltage of the at least two non-volatile memory cells from the erased state to a first program state among the plural program states and a single pulse program operation to increase a threshold voltage of at least one non-volatile memory cell among the at least two non-volatile memory cells from the first program state to another program state which is higher than the first program state among the plural program states.

Abstract: Provided is method and apparatus with memory array programming. A memory apparatus may include a memory array including memory cells, and a memory controller, where the memory controller is configured to configured to repeat, for a plurality of times, a generation of a first present time current error between a first present time current and a first target current, both of a first memory cell, a generation of a second present time current error between a second present time current and a second target current, both of a second memory cell, where a greatest among the first present time current error and the second present time current error is a greatest present time current error, and a programming of a select one of the first and second memory cells that has the greatest present time current error.

Abstract: An interface circuit that can operate in toggle mode at data high transfer rates while reducing the self-induced noise is presented. The high speed toggle mode interface supplies a data signal to a data line or other transfer line by a driver circuit. The driver circuit includes a pair of series connected transistors connected between a high supply level and a low supply level, where the data line is supplied from a node between the two transistors. A resistor is connected between one or both of the transistors and one of the supply levels, with a capacitor connected between the low supply level and a node between the resistor and the transistor. The resistor helps to isolate the transistor from the supply level while the capacitor can act as current reservoir to boost the current to the transistor during data transition, reducing the noise seen by the voltage supply.

Abstract: A nonvolatile memory device includes a first memory chip and a second memory chip connected to a controller through the same channel. The first memory chip generates a first signal from a first internal clock signal based on a clock signal received from the controller. The second memory chip generates a second signal from a second internal clock signal based on the clock signal, and performs a phase calibration operation on the second signal on the basis of a phase of the first signal by delaying the second internal clock signal based on a phase difference between the first and second signals.

Abstract: A phase-change memory (PCM) cell is provided to include a first electrode, a second electrode, and a phase-change feature disposed between the first electrode and the second electrode. The phase-change feature is configured to change its data state based on a write operation performed on the PCM cell. The write operation includes a reset stage and a set stage. In the reset stage, a plurality of reset current pulses are applied to the PCM cell, and the reset current pulses have increasing current amplitudes. In the set stage, a plurality of set current pulses are applied to the PCM cell, and the set current pulses exhibit an increasing trend in current amplitude. The current amplitudes of the set current pulses are smaller than those of the reset current pulses.

Abstract: A capacitor comprises a first electrode, a second electrode provided on the first electrode, a ferroelectric film provided between the first electrode and the second electrode, and a dielectric film provided between the ferroelectric film and the second electrode, impedance of the ferroelectric film and impedance of the dielectric film are determined such that a control voltage applied between the first electrode and the second electrode is equal to a capacitance boosting operating voltage, and the capacitance boosting operating voltage is determined by the following equation: V MAX = ( 1 + ? "\[LeftBracketingBar]" Z 2 ? "\[RightBracketingBar]" ? "\[LeftBracketingBar]" Z 1 ? "\[RightBracketingBar]" ) ? t F ? E FM where VMAX is a capacitance boosting operating voltage, Z1 is impedance of the ferroelectric film, Z2 is impedance of the dielectric film, tF is a thickness of the ferroelectric film, and EFM is an electric field applied to the ferroelectric film having a maximum