Abstract: A memory device includes a common source line, a memory cell array, bit lines, and a conductive layer. The common source line is formed on a substrate. The memory cell array is formed on the common source line. The bit lines are connected to the memory cell array. The conductive layer is formed over the bit lines. In an erase operation, the memory device increases a voltage of the bit lines to an erase voltage through capacitive coupling by increasing a voltage applied to the conductive layer.

Abstract: A memory device includes a memory cell array, a voltage switching circuit configured to switch a plurality of voltages provided to the memory cell array in response to a switching control signal, a discharge circuit configured to discharge the voltage switching circuit in response to a discharge signal, and a control circuit configured to generate the switching control signal based on a command and a high voltage enable signal received from outside of the memory device. The voltage switching circuit includes a high voltage switching circuit, and a low voltage switching circuit. The control circuit is configured to generate the discharge signal based on the command and an activated high voltage enable signal responsive to detecting external abortion while performing an operation corresponding to the command from among a program operation and an erase operation.

Abstract: Discussed herein are systems and methods for charging an access line to a non-volatile memory cell during a standby state, such as to prevent or mitigate standby-state charge loss. An embodiment of a memory device comprises a memory cell, a string driver circuit, and a charging circuit. The string driver circuit is coupled to the memory cell via a local word line, and has a common p-well. The charging circuit, in response to a voltage of a global word line of the memory device falling below a reference voltage during a standby state, couple a supply voltage to the common p-well of the string driver circuit to charge the global word line to a positive bias potential. The memory device includes a leakage compensation circuit to compensate for the junction leakage.

Abstract: A semiconductor memory apparatus may include a memory bank, a global buffer array, and an input and output circuit. The memory bank includes a local data circuit, and the global buffer array includes a global data circuit. The local data circuit is operably coupled to the global data circuit. The global buffer array may be operably coupled to the input and output circuit. The memory bank is disposed in a core region, and the global buffer array and the input and output circuit may be disposed in a peripheral region separated from the core region.

Abstract: A memory device that includes a first memory cell, a second memory cell and a sense amplifier. The sense amplifier includes a first branch and a second branch and are configured to output a first voltage and a second voltage to the first memory and the second memory, respectively in a trimming operation. A first clamp device of the sense amplifier includes a first clamp transistor and a plurality of first trimming transistors that are coupled to the first clamp transistor in parallel. The gate terminals of the first clamp transistor and the plurality of first trimming transistors are biased by a fixed clamp voltage. Each of the plurality of first trimming transistors is selectively conducted to compensate a mismatch between the first voltage and the second voltage.

Abstract: A processor-in-memory device includes a memory array, a sense amplifier, and a processing unit that has an accumulator. The processing unit is configured to receive a set of data. The processing unit then uses the sense amplifier and the accumulator to generate a first histogram of the set of data.

Abstract: Provided are a device comprising a bit cell tile including at least two memory cells, each of the at least two memory cells including a resistive memory element, and methods of operating an array of the memory cells, each memory cell including a resistive memory element electrically coupled in series to a corresponding first transistor and to a corresponding second transistor, the first transistor including a first gate coupled to a corresponding one of a plurality of first word lines and the second transistor including a second gate coupled to a corresponding one of a plurality of second word lines, each memory cell coupled between a corresponding one of a plurality of bit lines and a corresponding one of a plurality of source lines. The methods may include applying voltages to the first word line, second word line, source line, and bit line of a memory cell selected for an operation, and resetting the resistive memory element of the memory cell in response to setting the selected bit line to ground.

Abstract: A method includes identifying a target plane in respective planes of a memory die in a non-volatile memory array and identifying, from blocks of non-volatile memory cells coupled to a common bit line in the target plane, at least one target block in the target plane. The method further includes performing an operation to disable at least one gate associated with the at least one target block to prevent access to the blocks of non-volatile memory cells coupled to the common bit line in the target plane.

Abstract: Apparatuses, systems, and methods for voltage based random number generation. A memory may include a number of different voltages, which may be used to power various operations of the memory. During access operations to the memory, the voltage may vary, for example as word lines of the memory are accessed. The variability of the voltage may represent a source of randomness and unpredictability in the memory. A random number generator may provide a random number based on the voltage. For example, an analog to binary converter (ADC) may generate a binary number based on the voltage, and the random number may be based on the binary number.

Abstract: The present disclosure includes apparatuses and methods related to bank coordination in a memory device. A number of embodiments include a method comprising concurrently performing a memory operation by a threshold number of memory regions, and executing a command to cause a budget area to perform a power budget operation associated with the memory operation.

Abstract: A memory device includes a memory array of memory cells, wordlines and bitlines connected to the memory cells, a first read multiplexor and a second read multiplexor connected to the bitlines, a first sense amplifier connected to the first read multiplexor, a second sense amplifier connected to the second read multiplexor, a first data path connected to the first sense amplifier, and a second data path connected to the second sense amplifier. Each of the memory cells is connected to only one pair of the bitlines and only one of the wordlines. The first read multiplexor is adapted to connect the first sense amplifier to the bitlines during a first portion of a clock cycle and the second read multiplexor is adapted to connect the second sense amplifier to the bitlines during a second portion of a clock cycle that is different from the first portion of the clock cycle.

Abstract: A storage device may include a one time programmable (OTP) memory including a plurality of OTP cells and configured to store OTP key values in the plurality of OTP cells, and an erase instruction circuit that is detachably mounted on the storage device and connected to a first node of the OTP memory. When the erase instruction circuit is removed from the storage device, the OTP memory may be configured to receive the erase instruction signal having a first logic level at the first node and permanently erase all the OTP key values stored in the plurality of OTP cells by programming the plurality of OTP cells to an identical OTP key value in response to the erase instruction signal having the first logic level.

Abstract: A measure associated with a characteristic of a die of a memory device is obtained. It is determined whether the measure satisfies a first criterion to group one or more die into a first die family. If it is determined that the measure satisfies the first criterion, the die is associated with the first die family.

Abstract: Technology is disclosed herein for concurrently programming the same data pattern in multiple sets of non-volatile memory cells. Voltage are applied to bit lines in accordance with a data pattern. A select voltage is applied to drain select gates of multiple sets of NAND strings. The system concurrently applies a program pulse to control gates of a different set of selected memory cells in each respective set of the multiple sets of the NAND strings while the select voltage is applied to the drain select gates of the multiple sets of the NAND strings and the voltages are applied to the plurality of bit lines to concurrently program the data pattern into each set of the selected memory cells.

Abstract: An apparatus is provided that includes a plurality of non-volatile memory cells and a control circuit coupled to the non-volatile memory cells. The control circuit is configured to perform a first program-verify iteration on a first set of non-volatile memory cells coupled to a first word line to determine a first starting program voltage that programs the first set of the non-volatile memory cells to a first programmed state, and program a second set of non-volatile memory cells coupled to the first word line beginning with the first starting program voltage only if a defect condition does not exist.

Abstract: A memory device is provided. The memory device includes an array of memory cells arranged, a plurality of word lines, and a peripheral circuit configured to perform multi-pass programming on a selected row of memory cells coupled to a selected word line. The multi-pass programming includes a plurality of programming passes. Each of the programming passes includes a programming operation and a verify operation. To perform the multi-pass programming, the peripheral circuit is configured to, in a non-last programming pass of memory cells, perform a negative gate stress (NGS) operation on a memory cell in the selected row of memory cells between the programming operation and the verify operation; and at a same time, perform a NGS operation on a memory cell in an unselected row of memory cells coupled to an unselected word line of the word lines. The unselected word line is adjacent to the selected word line.

Abstract: A request to perform a secure erase operation for a memory component can be received. A voltage level that is applied to unselected wordlines of the memory component during a read operation can be determined. A voltage pulse can be applied to at least one wordline of the memory component to perform the secure erase operation. The voltage pulse can be associated with a program operation to place a memory cell of the memory component at another voltage level that exceeds the voltage level that is applied to the unselected wordlines of the memory component during the read operation.

Abstract: An integrated circuit memory device having: a memory cell; and a voltage driver of depletion type connected to the memory cell. In a first polarity, the voltage driver is powered by a negative voltage relative to ground to drive a negative selection voltage or a first de-selection voltage; In a second polarity, the voltage driver is powered by a positive voltage relative to ground to drive a positive selection voltage or a second de-selection voltage. The voltage driver is configured to transition between the first polarity and the second polarity. During the transition, the voltage driver is configured to have a control voltage swing for outputting de-selection voltages smaller than a control voltage swing for output selection voltages.

Abstract: A method for managing a memory apparatus comprising a plurality of NV memory elements is disclosed. The method includes providing a physical block of each NV memory element with a local page address linking table by obtaining a first host address and first data from a first host command, and obtaining a second host address and second data from a second host command; linking the first host address to a first page of the physical block; and linking the second host address to a second page of the physical block. A global page address linking table is built by reading the local page address linking tables and stored in a volatile memory. For the local page address linking table, a difference value of the first host address and the second host address is greater than a number of pages of the physical block.

Abstract: A temperature sensing circuit of a data storage system includes a temperature sensor, a digital-to-analog circuit, and a reference generation and trimming circuit configured to generate a common mode voltage (VCM), a positive reference voltage (VREFP), and a negative reference voltage (VREFN) using a single band gap reference signal. The trimming circuit is configured to trim the VCM, VREFP, and VREFN by adjusting a VC trim signal to increase the VCM until a VCM error is below a threshold; adjusting a high temperature trim signal to increase the VREFP and decrease the VREFN until a digital temperature signal associated with the digital-to-analog circuit attains a predetermined accuracy level for a first temperature; and adjusting a low temperature trim signal to increase the VREFP, VCM, and VREFN until the digital temperature signal attains a predetermined accuracy level for a second temperature.