Abstract: Disclosed herein is an apparatus that includes a memory cell array; a data input/output terminal; a read data path and a write data path coupled in parallel between the memory cell array and the data input/output terminal, wherein the read data path includes a pre-driver and an output driver coupled in series, and wherein the write data path includes an input receiver and a latch circuit coupled in series; and a test path configured to provide a shortcut between the pre-driver in the read data path and the latch circuit in the write data path.

Abstract: A method includes identifying a target plane in respective planes of a memory die in a non-volatile memory array and identifying, from blocks of non-volatile memory cells coupled to a common bit line in the target plane, at least one target block in the target plane. The method further includes performing an operation to disable at least one gate associated with the at least one target block to prevent access to the blocks of non-volatile memory cells coupled to the common bit line in the target plane.

Abstract: Endurance mechanisms are introduced for memories such as non-volatile memories for broad usage including caches, last-level cache(s), embedded memory, embedded cache, scratchpads, main memory, and storage devices. Here, non-volatile memories (NVMs) include magnetic random-access memory (MRAM), resistive RAM (ReRAM), ferroelectric RAM (FeRAM), phase-change memory (PCM), etc. In some cases, features of endurance mechanisms (e.g., randomizing mechanisms) are applicable to volatile memories such as static random-access memory (SRAM), and dynamic random-access memory (DRAM). The endurance mechanisms include a wear leveling scheme that uses index rotation, outlier compensation to handle weak bits, and random swap injection to mitigate wear out attacks.

Abstract: A voltage shift for memory cells of a block family at a memory device is measured. The block family is associated with a first voltage offset. An adjusted amount of voltage shift is determined for the memory cells based on the measured voltage shift and a temporary voltage shift offset associated with a difference between a current temperature and a prior temperature for the memory device. The block family is associated with a second voltage offset in view of the adjusted voltage shift.

Abstract: The storage device that includes a non-volatile memory with a control circuitry that is communicatively coupled to an array of memory cells that are arranged in a plurality of word lines. The control circuitry is configured to program the memory cells in a plurality of programming loops. The programming loops include applying a programming pulse to a selected word line of the plurality of word lines. The programming loops also include applying a verify pulse VN to the selected word line to simultaneously verify a lower tail of the memory cells being programmed to a data state N and an upper tail of the memory cells that have been programmed to a data state N?1. The data state N?1 has a lower voltage threshold than the data state N.

Abstract: Apparatuses and methods have been disclosed. One such apparatus includes a plurality of memory cells that can be formed at least partially surrounding a semiconductor pillar. A select device can be coupled to one end of the plurality of memory cells and at least partially surround the pillar. An asymmetric assist device can be coupled between the select device and one of a source connection or a drain connection. The asymmetric assist device can have a portion that at least partially surrounds the pillar and another portion that at least partially surrounds the source or drain connection.

Abstract: A method includes associating, by a processing device, a set of dies of a block family with a die family, wherein the block family is associated with a first threshold voltage offset bin for voltage offsets to be applied in a read operation; and responsive to detecting a triggering event, associating each die of the set of dies with a second threshold voltage offset bin for voltage offsets to be applied in a read operation, wherein the second threshold voltage offset bin is selected based on a representative die of the set of dies associated with the die family.

Abstract: A ferroelectric random access memory device comprises: a memory cell array including a plurality of memory cells each having one ferroelectric transistor (FeFET) connected between a read line of a plurality of read lines and a source line of a plurality of source lines and one transistor connected between a bit line of a plurality of bit lines and a gate of the FeFET and having a gate connected to a corresponding word line of a plurality of word lines; and a read/write control unit, when address information for a memory cell to be written is applied with a write command and data, selecting a word line and a read line corresponding to a row address and applying a write voltage having a positive voltage level, and applying a ground voltage to the selected read line, and applying the write voltage to a bit line corresponding to a memory cell.

Abstract: A method includes determining a first valid translation unit count (VTC) for a first block of memory cells, determining a second VTC for a second block of memory cells when the first VTC is below a VTC threshold corresponding to performance of a memory management operation, consolidating the first VTC and the second VTC when the consolidated first VTC and the second VTC equal or exceed the VTC threshold corresponding to the performance of the memory management operation, and executing the memory management operation utilizing the consolidated first VTC and the second VTC.

Abstract: Endurance mechanisms are introduced for memories such as non-volatile memories for broad usage including caches, last-level cache(s), embedded memory, embedded cache, scratchpads, main memory, and storage devices. Here, non-volatile memories (NVMs) include magnetic random-access memory (MRAM), resistive RAM (ReRAM), ferroelectric RAM (FeRAM), phase-change memory (PCM), etc. In some cases, features of endurance mechanisms (e.g., randomizing mechanisms) are applicable to volatile memories such as static random-access memory (SRAM), and dynamic random-access memory (DRAM). The endurance mechanisms include a wear leveling scheme that uses index rotation, outlier compensation to handle weak bits, and random swap injection to mitigate wear out attacks.

Abstract: A storage device includes a plurality of nonvolatile memory devices, a storage controller circuit and a leakage detection circuit. The storage controller circuit controls a plurality of nonvolatile memory devices, the storage controller circuit includes a plurality of connection terminals, each of the plurality of connection terminals is commonly connected to a corresponding set of pins, from among the pluralities of pins included in the plurality of nonvolatile memory devices, via a corresponding connection node, from among a plurality of connection nodes. The pins included in each set of pins have a same attribute. The leakage detection circuit is configured to determine whether leakage occurs at each set of pins based on the merged signal generated by the connection node connected to each set of pins, and configured to provide the storage controller circuit with a detection signal indicating a result of the determination.

Abstract: The present disclosure relates to a structure including a non-fixed read-cell circuit configured to switch from a first state to a second state based on a state of a memory cell to generate a sensing margin.

Abstract: Non-volatile memory systems and method for managing P/E cycling is disclosed. Memory systems include multi-plane (e.g., 2-plane or 4-plane) programming operations in which new blocks within a plane replace faulty/bad blocks. Existing blocks, having undergone several P/E cycles more than the new block(s), require a lower programming voltage and are programmed using an adaptive (reduced) programming voltage. New block(s) require an additional voltage, and a delta voltage is added to the programming voltage to increase the gate-to-channel voltage. To prevent the delta voltage from over-programming the existing blocks, a voltage equal to the delta voltage is applied bit lines of the existing blocks, thereby reducing the effective gate-to-channel voltage on the existing blocks.

Abstract: A liquid electrochemical memory device is provided. In one aspect, the device includes a memory region for storing at least two bits, the memory region having a first volume; and a liquid electrolyte region fluidically connected to the memory region, the liquid electrolyte region having a second volume larger than the first volume. The device further includes a working electrode exposed to the memory region, and a counter electrode exposed to the liquid electrolyte region. The device also includes an electrolyte filling the memory region and the liquid electrolyte region, in physical contact with the working electrode and the counter electrode, the electrolyte including at least two conductive species. The device further includes a control unit for biasing the working electrode and the counter electrode.

Abstract: A capacitor comprises a first electrode, a second electrode provided on the first electrode, a ferroelectric film provided between the first electrode and the second electrode, and a dielectric film provided between the ferroelectric film and the second electrode, impedance of the ferroelectric film and impedance of the dielectric film are determined such that a control voltage applied between the first electrode and the second electrode is equal to a capacitance boosting operating voltage, and the capacitance boosting operating voltage is determined by the following equation: V MAX = ( 1 + ? "\[LeftBracketingBar]" Z 2 ? "\[RightBracketingBar]" ? "\[LeftBracketingBar]" Z 1 ? "\[RightBracketingBar]" ) ? t F ? E FM where VMAX is a capacitance boosting operating voltage, Z1 is impedance of the ferroelectric film, Z2 is impedance of the dielectric film, tF is a thickness of the ferroelectric film, and EFM is an electric field applied to the ferroelectric film having a maximum

Abstract: According to one embodiment, three bits stored in one memory cell of a nonvolatile memory correspond to three pages. In first page writing, a threshold voltage becomes within a first or second region base on a bit value. In second page writing, if being within the first region, it becomes within the first or fourth region; and if being within the second region, it becomes within the second or third region. In the third page writing, if being within the first region, it becomes within the first or sixth region; if being within the second region, it becomes within the second or seventh region; if being within the third region, it becomes within the third or eighth region; and if being within the fourth region, it becomes within the fourth or fifth region.

Abstract: Systems and methods provide new circuits that increase aCAM precision by leveraging the concept of range segmenting to representationally store an analog voltage range across multiple aCAM cells/sub-circuits (here the representationally stored analog voltage range may correspond to a word entry). In this way, a circuit of the presently disclosed technology can increase precision (e.g., the number of programmable levels that can be used to store a word entry and/or the number of programmable levels that an input signal can be search against) linearly with each aCAM cell/sub-circuit added to the circuit. Accordingly, circuits of the presently disclosed technology can be used to carry out more complex computations than conventional aCAMs—and thus can be used in a wider range of computational applications.

Abstract: The present disclosure includes apparatuses and methods to transfer data between banks of memory cells. An example includes a plurality of banks of memory cells and a controller coupled to the plurality of subarrays configured to cause transfer of data between the plurality of banks of memory cells via internal data path operations.

Abstract: A method for managing a memory apparatus including a plurality of non-volatile (NV) memory elements includes: programming a physical block of a specific NV memory element, including: receiving a host command from a host; obtaining a host address and data from the host command; and linking the host address to a page of a physical block of the specific NV memory element and storing the data into the physical block. Before the pages of the physical block are fully programmed, a temporary local page linking address table is stored and is updated each time a linking relationship is changed. When the memory apparatus is to be shut down, the temporary local page linking address table is written to the specific NV memory element; and when the memory apparatus begins a start-up process, a global page address linking table is built by reading the local page address linking table.

Abstract: Various implementations described herein are related to a device having memory circuitry having an array of memory cells. The device may include output circuitry coupled to the memory circuitry, and the output circuitry may have a first set of multiplexers that receives column data from the array of memory cells and provides first multiplexed output data. The device may include output interface circuitry coupled to the output circuitry, and the output interface circuitry may have a second set of multiplexers that receives the first multiplexed output data from the output circuitry and selectively provides second multiplexed output data based on a configurable mode of multiplexed operation.