Abstract: A random code generator includes a differential cell array, a power supply circuit, a first selecting circuit and a current judgment circuit. The power supply circuit receives an enrolling signal and a feedback signal. The first selecting circuit receives a first selecting signal. When the enrolling signal is activated and an enrollment is performed on the first differential cell, the power supply circuit provides an enrolling voltage, and the enrolling voltage is transmitted to a first storage element and a second storage element of the first differential cell through the first selecting circuit. Consequently, the cell current is generated. When a magnitude of the cell current is higher than a specified current value, the current judgment circuit activates the feedback signal, so that the power supply circuit stops providing the enrolling voltage.

Abstract: A semiconductor device capable of automatically transitioning from a standby mode to a deep power down (DPD) mode is provided. The semiconductor device includes: internal circuits capable of operating in response to an input signal from an input/output circuit; and a controller capable of controlling operations of the internal circuits. The internal circuit supporting the DPD mode includes: a measurement part, measuring a time since a time point of the semiconductor device entering the standby mode; a transition time detection part, detecting a case where a measurement time of the measurement part has reached a certain time; and a DPD signal generation part, generating a power down enable signal for further reducing power consumption in the standby mode when a transition time is detected.

Abstract: A processing device of a memory sub-system is configured to detect a power on event associated with the memory device; scan one or more blocks of a plurality of blocks of the memory device to determine a corresponding time after program (TAP) associated with each block of the one or more blocks; estimate, based on the corresponding TAP of the each block of the one or more blocks, a duration of a power off state preceding the power on event; and update voltage bin assignments of the plurality of blocks associated with the memory device based on the duration of the power off state.

Abstract: Various implementations described herein refer to an integrated circuit having a memory cell array with a first number of rows and a second number of rows. The integrated circuit may include a first pre-decoder that receives a row address and selects a first row from the first number of rows based on the row address. The integrated circuit may include a second pre-decoder that receives the row address from the first pre-decoder and selects a second row from the second number of rows based on the row address received from the first pre-decoder. The integrated circuit may include a single row decoder that receives the row address and selects either the first row or the second row based on a row selection bit from the row address.

Abstract: Provided herein may be a memory device having improved overshoot management performance, and a method of operating the memory device. The method may include: applying a select voltage to a select line coupled in common to respective select transistors in a plurality of cell strings; and applying a program voltage to a selected word line coupled in common to selected memory cells among a plurality of memory cells in the plurality of cell strings. The applying of the select voltage may include applying a first select voltage to the select line during a first time period. The applying of the program voltage may include applying, to the select line, a second select voltage having a voltage level higher than a voltage level of the first select voltage.

Abstract: Ternary content-addressable memory (TCAM) devices are described. The TCAMs described herein are designed to perform write operations—including data writes and mask writes—in a single clock cycle. For example, data input is written in a row of the TCAM during the first portion of a clock cycle, and a mask is written in another row of the TCAM during the second portion of the clock cycle. In one implementation, a first bus is used both for data write and key search operations, and a second bus is used both for mask write and search masking operations. In another implementation, a first bus is used both for data write and key search operations, a second bus is used for mask write operations, and a third bus is used for search masking operations.

Abstract: A method includes determining a first valid translation unit count (VTC) for a first block of memory cells, determining a second VTC for a second block of memory cells when the first VTC is below a VTC threshold corresponding to performance of a memory management operation, consolidating the first VTC and the second VTC when the consolidated first VTC and the second VTC equal or exceed the VTC threshold corresponding to the performance of the memory management operation, and executing the memory management operation utilizing the consolidated first VTC and the second VTC.

Abstract: A system can include a memory device and a processing device to perform operations that include performing a block family calibration scan of the memory device, wherein the calibration scan comprises a plurality of scan iterations, wherein each scan iteration is initiated in accordance with at least one threshold scan criterion, and wherein each scan iteration comprises identifying at least one first voltage bin, wherein each first voltage bin is associated with a plurality of read level offsets, identifying, according to a block family creation order, an oldest block family from a plurality of block families associated with the first voltage bin, and updating at least one bin pointer of the oldest block family based on a data state metric of at least one block of the oldest block family.

Abstract: A power control method for a memory storage device and a memory storage system are provided. The method includes configuring a power controller in a host system, controlling, by the power controller, a power gate disposed between the host system and the memory storage device, and controlling a power supply of the memory storage device from the host system by the power gate, wherein the power gate is not controlled by a Basic Input Output System (BIOS) controller of the host system.

Abstract: Methods of peak power management (PPM) for a memory chip having multiple memory dies are disclosed. Each memory die includes a first PPM circuit and a second PPM circuit. First PPM circuits of the multiple memory dies are electrically connected to form a first PPM group. Similarly, second PPM circuits are electrically connected to form a second PPM group. Peak power operations can be managed by switching on a first pull-down driver of the first PPM circuit on a selected memory die when a first PPM enablement signal of the first PPM group is zero; waiting for a first delay period; switching on a second pull-down driver of the second PPM circuit on the selected memory die when a second PPM enablement signal of the second PPM group is zero. The first and second PPM enablement signals depend on the current flowing through each pull-down driver in the first and second PPM groups.

Abstract: A semiconductor device capable of monitoring a connection state of a terminal on a semiconductor chip includes a selector configured to acquire terminal levels of a plurality of respective terminals on the semiconductor chip to which an inspection pattern is inputted based on a detection signal, a memory configured to store latch data based on a chip address which identifies the semiconductor chip and a plurality of the terminal levels corresponding to the plurality of terminals based on the detection signal, an output circuit configured to read a plurality of pieces of latch data from the memory based on the detection signal and to output the plurality of pieces of latch data, and a timing control circuit configured to generate the detection signal by detecting an edge of a clock inputted during an inspection mode and configured to activate the selector, the memory, and the output circuit.

Abstract: Storage devices are capable of utilizing failed bit count (FBC) reduction devices to reduce FBCs for word lines in blocks. An FBC reduction device may include a FBC count component, a threshold component, a pre-verify component, and a soft program component. The FBC count component may access the FBC for the word line, where the block has unprogrammed word lines in an unprogrammed region separated from programmed word lines of a programmed region by the word line. The threshold component may determine whether the FBC of the word line exceeds a predetermined threshold. When the FBC exceeds the threshold, the pre-verify component may perform pre-verify operations on the programmed region. The soft program component may program the word line with first data equal to second data programmed in a second block. In response to disabling pre-verify operations, the program component may program the unprogrammed word lines in the unprogrammed region.

Abstract: A non-volatile memory device including an array of memory cells coupled to word lines and a row decoder, which includes a first and a second pull-down stage, which are arranged on opposite sides of the array, and include, respectively, for each word line, a corresponding first pull-down switching circuit and a corresponding second pull-down switching circuit, which are coupled to a first point and a second point, respectively, of the first word line. The row decoder moreover comprises a pull-up stage, which includes, for each word line, a corresponding pull-up switching circuit, which can be electronically controlled in order to: couple the first point to a supply node in the step of deselection of the word line; and decouple the first point from the supply node in the step of selection of the word line.

Abstract: Discussed herein are systems and methods for protecting against transistor degradation in a high-voltage (HV) shifter to transfer an input voltage to an access line, such as a global wordline. An embodiment of a memory device comprises memory cells and a HV shifter circuit that includes a signal transfer circuit, and first and second HV control circuits. The signal transfer circuit includes a P-channel transistor to transfer a high-voltage input to an access line. The first HV control circuit couples a bias voltage to the P-channel transistor for a first time period, and the second HV control circuit couples a stress-relief signal to the P-channel transistor for a second time period, after the first time period, to reduce degradation of the P-channel transistor. The transferred high voltage can be used to charge the access line to selectively read, program, or erase memory cells.

Abstract: A system may include multiple memory cells to store logical data, age tracking circuitry to track a time since a previous access of a particular memory cell, and control circuitry to access the memory cell. Such access may include a read operation of the memory cell, a write operation to the memory cell, or both. The control circuitry may determine an electrical parameter of the memory cell based at least in part on the tracked time since the previous access of the memory cell.

Abstract: Methods, systems, and devices for memory accessing with auto-precharge are described. For example, a memory system may be configured to support an activate with auto-precharge command, which may be associated with a memory device opening a page of memory cells, latching respective logic states stored by the memory cells at a row buffer, writing logic states back to the page of memory cells, and maintaining the latched logic states at the row buffer (e.g., while maintaining power to latches of the row buffer, after closing the page of memory cells, while the page of memory cells is closed).

Abstract: A memory device having a plurality of memory blocks compensates for a characteristic change of a memory cell due to stopping an erase operation. The memory device also includes a voltage generator configured to generate voltages used by the memory device in performing an erase operation on a selected memory block among the plurality of memory blocks. The memory device further includes an erase stop controller configured to control stopping and resuming the erase operation, and counting the number of times the erase operation is stopped to generate a stop count value when the erase operation is stopped. The memory device additionally includes a count value storage configured to store and output the stop count value.

Abstract: A method for performing a read operation of a memory block of a read-only memory array, wherein the method comprises first enabling bit line precharge circuitry of the memory block, (thereby precharging one or more bit lines of the memory block to a first voltage level), enabling a word line of one or more addressed memory cells of the memory block, enabling a leakage current reduction circuit of the memory block, thereby generating across the addressed memory cells a first voltage differential equal to the first voltage level; subsequently discharging the addressed memory cells; disabling the word line of the one or more addressed memory cells; disabling the bit line precharge circuitry; and disabling the leakage current reduction circuit, thereby generating across the one or more addressed memory cells a second voltage differential that is equal to less than the first voltage differential.

Abstract: Disclosed herein is an apparatus that includes a memory cell array; a data input/output terminal; a read data path and a write data path coupled in parallel between the memory cell array and the data input/output terminal, wherein the read data path includes a pre-driver and an output driver coupled in series, and wherein the write data path includes an input receiver and a latch circuit coupled in series; and a test path configured to provide a shortcut between the pre-driver in the read data path and the latch circuit in the write data path.

Abstract: To improve the erase process, multiple methods of erasing are utilized. A first method of erasing is relied on at the beginning of life of the memory system. A second method is increasingly relied on as the memory system is used and undergoes many program/erase cycles. In one example, the first method of erase includes applying an erase enable voltage separately to different subsets of the word lines while word lines not receiving the erase enable voltage receive an erase inhibit voltage. In one example, the second method of erase includes applying an erase enable voltage concurrently to all subsets of the word lines.