Abstract: An apparatus and associated method are provided involving a housing having a periphery configured to operate as a second antenna, a third antenna, and a fourth antenna. The periphery includes a top wall having a first slot formed therein, a first side wall having a second slot formed therein, and a second side wall having a third slot formed therein. The top wall is arranged between the first side wall and the second side wall, and a top portion of the periphery is defined between the second slot and the third slot. The top portion is divided into a first top side portion and a second top side portion via the first slot. Further, the first top side portion operates as the second antenna, and the second top side portion operates as both the third antenna and the fourth antenna.

Abstract: A method can include, amplifying an analog input signal to generate an amplified analog signal; modulating the amplified analog signal into a digital data stream; filtering the digital data stream with a first digital filter to generate a first filtered data stream, and selectively changing a gain of the amplifier in response to the first filtered data stream. While the digital data stream is filtered with the first digital filter, the digital data stream is filtered with a second digital filter to generate a second filtered data stream. An output digital value corresponding to the analog input signal in response to the second filtered data stream. Corresponding systems and devices are also disclosed.

Abstract: An analog-to-digital converter (ADC) includes a modulator configured to oversample an input signal generated from an output signal of a transducer; and a filter configured to perform a decimation operation on an output from the modulator and a frequency characteristics correction operation according to a filter control signal on the output from the modulator, wherein the frequency characteristics correction operation is performed to complement a frequency characteristics of the output signal of the transducer such that overall frequency characteristics of the transducer and the filter be flat in a signal band.

Abstract: An IC can include shared reference voltage buffer circuitry having an amplifier circuit. A commonly-routed amplifier shared output voltage node can be shared between at least two digital-to-analog converters (DACs) respectively via at least first and second individually routed traces from the shared output voltage node to respective first and second local reference voltage nodes at the DACs. Respective first and second routing trace resistances can be based on current draw of the corresponding DAC, such as to provide an equal voltage drop across the first and second routing resistances. This can help avoid voltage contention or conflict at the shared output voltage node from forcing/sensing the voltages at the first and second local reference voltage nodes. In a further example, at least one of the first and second individually routed traces can include a binary tree hierarchical routing arrangement of at least some of the DACs.

Abstract: Methods, devices and systems for a compressor and a decompressor for encoding and decoding data in the cache/memory/data transferring subsystem in a computer system or in a communication network are described herein. An example variable-length compressor is able to compress blocks of data values and the compressed blocks may include mixes of compressed and uncompressed values, wherein metadata in the form of a unique special-meaning codeword (UUIC) indicates uncompressed values. An example variable-length decompressor is able to decompress the compressed data blocks. The compressor and decompressor are able to support compression and decompression of common compression scenarios that are used in combination with variable-length compression to improve compressibility in the cache/memory/data transferring subsystem in a computer system or in a communication network.

Abstract: A digital-to-analog converter (DAC) is described having a digital input, an analogue output, and two capacitors. The DAC has a controller. The controller is configured to generate a switching sequence including at least two switch cycles dependent on the input value received on the digital input. If the input value corresponds to an odd number, in a first switch cycle during a switch cycle first phase, the controller switchably couples a reference voltage to a first terminal and a ground voltage to a second terminal of one of the two capacitors, and switchably couples a ground voltage to a first terminal and the reference voltage to a second terminal of the other of the two capacitors. During a switch cycle second phase, the controller switchably couples a ground voltage to the first terminal and the analogue output to the second terminal of both capacitors.

Abstract: Methods, devices and systems for a compressor and a decompressor for encoding and decoding data in the cache/memory/data transferring subsystem in a computer system or in a communication network are described herein. Example variable-length compressors and decompressors are able to: compress more densely when specific values occur in specific positions in a data block; to improve compression and decompression latency when specific values that appear frequently occur in a data block; to also improve decompression latency by recording the lengths of variable-length encoded values of a compressed data block. The compressor and decompressor are able to support compression and decompression of common compression scenarios that are used in combination with variable-length compression to improve compressibility in the cache/memory/data transferring subsystem in a computer system or in a communication network.

Abstract: Facilitating energy-efficient wireless communications for advanced networks (e.g., 4G, 5G, and beyond) with low-resolution digital-to-analog converters is provided herein. Operations of a system can comprise determining first values. Respective values of the first values can be digital samples of transmission and reception chains determined based on symbols transformed from bits. The operations can also comprise facilitating a quantization of the first values resulting in second values. Facilitating the quantization can be based on a cost function associated with processing the first values. Further, the operations can comprise outputting the second values as a continuous time signal over antennas of a base station device. The second values can comprise fewer values than the first values.

Abstract: An inexpensive electronic control device is implemented that enables a power supply voltage supplied to a microcomputer to be varied using a simple method and that enables an identical power supply to be adapted to various microcomputers. A switch is turned on to determine the value of a discrete resistor, and a voltage based on the value of current from a current source and the resistance value of the discrete resistor is caused in an In1 terminal. By an A/D converter, the In1 terminal voltage is subjected to A/D conversion, and a digital code corresponding to the selectively connected discrete resistor is detected. The result of the A/D conversion is saved in a register, and the determination of the resistance value of the discrete resistor performed by the A/D converter is completed. After the completion of the resistance value determination performed by the A/D converter, power supply voltages start activation.

Abstract: A memory system includes a nonvolatile memory, an interface circuit, and a controller configured to upon receipt of a plurality of write commands for storing write data in the nonvolatile memory via the interface circuit, acquire compression-ratio information about the write data associated with each write command, determine a compression ratio of each write data based on the acquired compression-ratio information, and determine an execution order of the write commands based on the determined compression ratio.

Abstract: This application relates to time-encoding modulators (TEMs). A TEM receives an input signal (SIN) and outputs a time-encoded output signal (SOUT). A filter arrangement receives the input signal and also a feedback signal (SFB) from the TEM output, and generates a filtered signal (SFIL) based, at least in part, on the feedback signal. A comparator receives the filtered signal and outputs a time-encoded signal (SPWM) based at least in part on the filtered signal. The time encoding modulator is operable in a first mode with the filter arrangement configured as an active filter and in a second mode with the filter arrangement configured as a passive filter. The filter arrangement may include an op-amp, capacitance and switch network. In the first mode the op-amp is enabled, and coupled with the capacitance to provide the active filter. In the second mode the op-amp is disabled and the capacitance coupled to a signal path for the feedback signal to provide a passive filter.

Abstract: Analog multipliers can perform signal processing with approximate precision asynchronously (clock free) and with low power consumptions, which can be advantageous including in emerging mobile and portable artificial intelligence (AI) and machine learning (ML) applications near or at the edge and or near sensors. Based on low cost, mainstream, and purely digital Complementary-Metal-Oxide-Semiconductor (CMOS) manufacturing process, the present invention discloses embodiments of current-mode analog multipliers that can be utilized in multiply-accumulate (MAC) signal processing in end-application that require low cost, low power consumption, (clock free) and asynchronous operations.

Abstract: A wireless communication device converts a signal component, which has one of distributed frequency bands in an analog RF signal and passes through one of a plurality of bandpass filters, into digital data with an AD converter that carries out undersampling. A sampling frequency of the AD converter is set so that frequencies which are integral multiples of a Nyquist frequency based on the sampling frequency do not fall within frequency bands of signal components which are of the RF signal and are to pass through the respective plurality of bandpass filters.

Abstract: A multi-stage analog-to-digital converter (ADC) suitable for low power applications, such as glucose monitoring, may be required to digitize a slow-moving signal. As such, a multi-stage ADC must be versatile. Accordingly, the multi-stage ADC can be configured to operate at different bandwidths and resolutions through the use of ADC stages that can be enabled or disabled in an exchange between resolution and speed. Each ADC stage digitizes an input signal (e.g., a voltage or a current) using an analog comparison to access a lookup table for a digital signal that represents the input signal at a particular accuracy. Unlike other multi-stage approaches, the digitization is asynchronous (i.e., requires no clock) and can provide simplicity, speed, and low-power operation to the multi-stage ADC.

Abstract: A signal acquisition or conditioning amplifier can be configured and controlled to use correlated doubling sampling (CDS) of a differential input signal, and a storage capacitor in a capacitive or other feedback network, a low power operational transconductance amplifier (OTA) capable of being powered down between CDS samplings, and which can be operated in a manner that provides good performance characteristics while still providing low or efficient power consumption. The amplifier and other signal processing circuitry can allow power to be scaled down, when less signal measurement throughput is needed, and to be scaled up, when more signal measurement throughput is needed. Such flexibility can help make the present approach useful for a wide range of signal acquisition and measurement applications. Precharging via buffer amplifiers can provide improved signal acquisition circuitry effective input impedance.

Abstract: A device for noise suppression and distortion correction of analog-to-digital converters based on deep learning that realizes effect of correcting noise and distortion of analog to digital converters. The method is applied to electronic ADCs or photonic ADCs. It utilizes the learning ability of the deep network to perform system response learning on ADCs which need noise suppression and distortion correction, establishes a computational model in the deep network that can suppress the reconstruction of noises and distorted signals, performs noise suppression and distortion correction on the signals obtained by ADCs, and thereby improves performance of the learned ADCs. The device improves the performance of the microwave photon system with high sampling precision of microwave photon radar and optical communication system.

Abstract: A current integrator includes an operational amplifier, an integration capacitor and an offset cancelation capacitor. The operational amplifier includes a first input stage and a second input stage. The first input stage is coupled to an input terminal of the current integrator. The integration capacitor is coupled between the first input stage of the operational amplifier and an output terminal of the current integrator. The offset cancelation capacitor is coupled to the second input stage of the operational amplifier.

Abstract: A circuit includes a voltage-to-time conversion element configured to receive an input voltage at an input and to generate a time domain representation of the input voltage. The voltage-to-time conversion element includes an amplifier having an amplifier input coupled to the input, a zero crossing detector coupled to an output of the amplifier, and a current source selectively coupled to the amplifier input by way of a switching element.

Abstract: A parallel-to-serial conversion circuit may include first to fourth data lines; first to fourth parallel-to-serial converters configured to parallel-to-serial convert data of corresponding two data lines, among the first to fourth data lines, at a ratio of 2:1, respectively; and first to fourth drivers configured to transmit converted data of corresponding parallel-to-serial converter, among the first to fourth parallel-to-serial converters, respectively, to an output line, wherein two of the first to fourth drivers are simultaneously activated.

Abstract: A method of operating a redundant successive approximation analog-to-digital converter (ADC) includes: sampling an input signal; and successively approximating the sampled input signal using a digital-to-analog converter (DAC) including DAC reference elements having at least one sub-binary weighted DAC reference element. Successively approximating the sampled input signal includes performing a plurality of successive approximation cycles.