Abstract: A time-multiplexed group of MAC circuits for a machine learning application is provided in which at least one MAC circuit in the time-multiplexed group also functions as a capacitive-digital-to-analog converter (CDAC) within a successive approximation analog-to-digital converter (ADC). A comparator in the ADC is shared by the time-multiplexed group of MAC circuits.

Abstract: A device for monitoring voltage in a battery-operated system, the device including: a ladder selector configured to select between a first resistive ladder and a second resistive ladder; the first resistive ladder includes: a first string of resistors coupled between a sensing input node and a first node of the ladder selector; and a first set of transistors configured to tap intermediate nodes of a set of resistors in the first string of resistors; the second resistive ladder includes: a second string of resistors coupled between the sensing input node and a second node of the ladder selector; and a second set of transistors configured to tap intermediate nodes of a set of resistors in the second string of resistors; and wherein a selected transistor in one of the first set of transistors or the second set of transistors is turned on, and non-selected transistors of the first set of transistors and the second set of transistors are turned off to set a threshold voltage for a sensing output node.

Abstract: An imaging device for improving the determining speed of a comparator and reducing power consumption. The comparator imaging device includes a differential input circuit that operates with a first power supply voltage, the differential input circuit outputs a signal when an input signal is higher than a reference signal in voltage, and a positive feedback circuit that operates with a second power supply voltage lower than the first power supply voltage. The positive feedback circuit accelerates transition speed when a compared result signal indicating a compared result between the input signal and the reference signal in voltage, is inverted, on the basis of the output signal of the differential input circuit. The imaging device further includes a voltage conversion circuit that converts the output signal of the differential input circuit into a signal corresponding to the second power supply voltage.

Abstract: Systems and methods are described for determining a phase measurement difference between a received modulated signal and a local clock signal. An adjusted local clock phase measurement may be determined by subtracting, from the phase measurement difference, a phase correction that is based on the frequency difference between the modulator signal's carrier frequency and the local clock's frequency. A phase modulation value may be generated by scaling the adjusted local clock phase measurement. The scaling may be based on a ratio of the modulated signal's carrier frequency and the local clock's frequency. The phase correction may be based on (i) a count of periods of the modulated signal occurring between each corrected phase measurement and (ii) a difference between the carrier frequency and the local clock frequency.

Abstract: A digital-to-analog converter circuit including one or more digital-to-analog converter cells and a separate voltage protection circuit connected by a common output node. A first digital-to-analog converter cell includes a first transistor which is configured to be switched to a conductive state when the first digital-to-analog converter cell is activated. A first terminal of the first transistor is coupled to a defined potential, wherein a second terminal of the first transistor is coupled to a common output node of the one or more digital-to-analog converter cells. The digital-to-analog converter circuit further includes a voltage protection circuit coupled between the common output node of the one or more digital-to-analog converter cells and an output node of the digital-to-analog converter circuit to regulate a voltage between the common output node and the defined potential.

Abstract: In an embodiment, a method includes: providing a gray-coded time reference to a time-to-digital converter (TDC); receiving an event from an event signal; latching the gray-coded time reference into a memory upon reception of the event signal; and updating a time-of-flight (ToF) histogram based on the latched gray-coded time reference.

Abstract: An analog-to-digital converter (“ADC”) includes an input terminal configured to receive an analog input voltage signal. A first ADC stage is coupled to the input terminal and is configured to output a first digital value corresponding to the analog input voltage signal and a first analog residue signal corresponding to a difference between the first digital value and the analog input signal. An inverter based residue amplifier is configured to receive the first analog residue signal, amplify the first analog residue signal, and output an amplified residue signal. The amplified residue signal is converted to a second digital value, and the first and second digital values are combined to create a digital output signal corresponding to the analog input voltage signal.

Abstract: A signal processing structure and method are presented. A first digital filter operates on received sigma-delta modulated (SDM) input signals. A second pre-processing digital filter receives a SDM input signal, directly low pass filter the SDM input signal and provides an output SDM signal. The output sigma-delta modulated signal is provided as an input for said first digital filter. In standard digital systems operating with digital microphones, filtering of the microphones' output signal requires to first convert the signal into pulse code modulation (PCM), then filter and finally convert back to pulse density modulation (PDM). This approach increases the latency of the system because decimation and interpolation must be performed in order to pass from PDM to PCM. By using filters that operate directly on the oversampled PDM output of the digital microphones it is possible to reduce the latency of the system and minimize the hardware area.

Abstract: A sensor arrangement includes a sensor having a first terminal and a second terminal, and an amplifier having an amplifier input for applying an input signal and an amplifier output for providing an amplified input signal, the amplifier input being coupled to the second terminal. A quantizer having a quantizer input and a quantizer output is configured to provide a multi-level output signal on the basis of the amplified input signal and a feedback circuit having a feedback circuit input coupled to the quantizer output and a feedback circuit output coupled to the first terminal. The feedback circuit includes a digital-to-analog converter configured to generate an analog signal on the basis of the multi-level output signal, the analog signal being the basis of a feedback signal provided at the feedback circuit output, a feedback capacitor coupled between the feedback circuit output and an output of the digital-to-analog converter, and a voltage source coupled to the feedback circuit output.

Abstract: A successive approximation register analog-to-digital converter includes a comparator circuit, a capacitor group, an additional capacitor and a control circuit. The comparator circuit compares voltages at first and second input terminals thereof to generate a comparison result. The capacitor group and the additional capacitor are coupled to the first input terminal. The control circuit controls voltages of capacitors of the capacitor group according to the comparison result. In a first period, the control circuit provides a first voltage to the first input terminal and the additional capacitor, and provides an analog signal to the capacitors. In a second period, the control circuit stops providing the first voltage and controls a specific capacitor of the capacitor group to enter into a floating state. In a third period, the control circuit provides a second voltage to the additional capacitor. The second voltage is lower than the first voltage.

Abstract: A capacitance-to-digital converter and an associated method and computer program product are provided that have an extended measurement range. A capacitance-to-digital converter includes first and second capacitors with the second capacitor being configured to measure a change in a value. The capacitance-to-digital converter also includes first and second switches switchably connecting the first and second capacitors, respectively, to a reference voltage while the first and second switches are in a first position such that charge is stored by the first and second capacitors in response to the reference voltage. The capacitance-to-digital converter further includes a saturation detector configured to detect the charge stored by the second capacitor equaling or exceeding the charge stored by the first capacitor and, in response, causing the first and second switches to switch to a second position while continuing to measure the change in the value with the charge stored by the second capacitor.

Abstract: A time-interleaved digital-to-analog converter (DAC) includes a digital processing circuit, a time-domain dynamic element matching (TDEM) circuit, a plurality of DACs, and a combining circuit. The digital processing circuit generates data sequences according to the digital signal. The data sequences include a first data sequence and a second data sequence. The TDEM circuit swaps a portion of the first data sequence with a portion of the second data sequence to generate a first adjusted data sequence and a second adjusted data sequence. The DACs include a first DAC and a second DAC. The first DAC has a first DAC cell that operates in response to the first adjusted data sequence. The second DAC has a second DAC cell that operates in response to the second adjusted data sequence. The combining circuit generates the analog signal by combining analog outputs of the DACs.

Abstract: A method of encoding fixed length data bit strings includes receiving and sequentially encoding a sequence of data bit strings. For a data bit string immediately following a preceding data bit string, this includes obtaining a reference bit string, and a mask bit string and a tracking bit string as present at the end of a previous encoding of the preceding data bit string, identifying bits that differ form corresponding bits in the reference bit string, determining, as unpredictable bits, all those bits in the data bit string that are indicated as not predictable by the mask bit string and are not in bit positions indicated by the tracking bit string, generating a sequence of position indicators, generating an encoded data packet that includes representations of values of the unpredictable bits and the sequence of positon indicators, and periodically updating the mask bit string and the tracking bit string.

Abstract: Compressed domain processors configured to perform operations on data compressed in a format that preserves order. The Compressed domain processors may include operations such as addition, subtraction, multiplication, division, sorting, and searching. In some cases, compression engines for compressing the data into the desired formats are provided.

Abstract: In certain aspects, a circuit for modulo-3 operation has an encoder stage coupled to a binary number, wherein the encoder stage includes one or more encoders, each one of the one or more encoders receives one or two binary bits of the binary number and generates a unary code of encoder. The circuit for modulo-3 operation further has one or more levels of reduction stage, wherein a first level of the one or more levels of reduction stage includes one or more mergers of first reduction, each one of the one or more mergers of first reduction receives two unary codes of encoder or a unary code of encoder and a bit from the binary number and generates a unary code of first reduction.

Abstract: A SAR ADC may include a plurality of capacitor networks, wherein each capacitor network of the plurality of capacitor networks has a sampling capacitor for sampling an analog input signal to the SAR ADC and at least one non-sampling capacitor. The SAR ADC may also include a DAC including a plurality of sub-DACs including at least a first sub-DAC representing most significant bits of an output of the SAR ADC, wherein the output of the first sub-DAC is coupled to the sampling capacitors of the plurality of capacitor networks and a second sub-DAC representing bits of the output of the SAR ADC lesser in magnitude significance than those of the first sub-DAC, wherein the output of the second sub-DAC is coupled to a respective one of at least one non-sampling capacitor of each of the plurality of capacitor networks.

Abstract: A method for efficient name coding in a storage system is provided. The method includes identifying common prefixes, common suffixes, and midsections of a plurality of strings in the storage system, and writing the common prefixes, midsections and common suffixes to a string table in the storage system. The method includes encoding each string of the plurality of strings as to position in the string table of prefix, midsection and suffix of the string, and writing the encoding of each string to memory in the storage system for the plurality of strings, in the storage system.

Abstract: A semiconductor device includes a signal input circuit configured to select one of the plurality of differential sensor signals according to a channel selection signal; an amplifier circuit configured to amplify an output of the signal input circuit; and an analog-to-digital converter (ADC) configured to convert an output of the amplifier circuit into a digital value, wherein each of the plurality of sensor signals is a differential signals and the signal input circuit changes polarity of an output signal thereof according to a first chopping signal, and wherein the ADC includes a delta-sigma modulator configured to generate a bit stream from an output of the amplifier circuit; an output chopping circuit configured to adjust phase of the bit stream according to the first chopping signal; and a filter configured to filter an output of the output chopping circuit and to output the digital value.

Abstract: A new SARADC has two low resolution SAR (Successive Approximation Register) ADCs coupled together by an amplifier to increase the overall resolution and enhance ADC conversion rate. The gain reduction of amplifier is corrected by shifting the digital binary output position. Two SAR ADC outputs are timing aligned and summed to produce final high-resolution high conversion rate ADC output.

Abstract: A code decompression engine reads compressed code from a memory containing a series of code parts and a dictionary part. The code parts each have a bit indicating compressed or uncompressed. When the code part is compressed, it has a value indicating the number of segments, followed by the segments, followed by an index into the dictionary part. The decompressed instruction is the dictionary value specified by the index, which is modified by the segments. Each segment describes the modification to the dictionary part specified by the index by a mask type, a mask offset, and a mask.