Abstract: A technique provides data from an information signal. The technique involves receiving the information signal in the forwarded clock device synchronously with a forwarded clock signal. The technique further involves recovering data contained within the information signal synchronously with a recovery clock signal such that the data is recovered with (i) a particular cycle latency when the recovery clock signal has an optimal rate for the forwarded clock device, and (ii) a different cycle latency when the recovery clock signal has a sub-optimal rate. The particular cycle latency may include more cycles than the different cycle latency. As such, the time latency may be shorter when the recovery clock signal has the sub-optimal rate.

Abstract: In a data communications system, a digitally implemented correction for baseline wander and the receipt of killer packets resulting from coupling transformers in the transmission channel is presented. The baseline wander correction is accomplished in a feedback loop that does not depend on models of the coupling transformers between the transmitter and the transport media and the receiver and the transport media. Additionally, a digital response to killer packets is presented that does not require the use of higher resolution analog-to-digital converters and does not require the use of a lower resolution in the analog-to-digital converter of the receiver. Instead, the reference voltage of the analog-to-digital converter is adjusted for short cables, where killer packets are a problem.

Abstract: Circuits and methods are described which reduce waiting time jitter at a synchronizer/multiplexer by using a “sub-bit” comparison of a clock associated with an unsynchronized data stream and a clock associated with a synchronized data stream to generate a threshold level for use in determining when to stuff bits into the synchronized data stream. The term “sub-bit” means that the phase difference, as measured by, for example, the location of pointers associated with the two clocks, is precise to a fraction of a bit.

Abstract: A modem system utilizes PCM encoding and transmission techniques in the upstream direction from a client modem (connected to a digital network via an analog loop) to a central site modem (connected to the digital network via a digital link). The modem system employs precoding techniques that enable the transmit signal to be pre-equalized to compensate for the analog channel characteristics. The precoding technique generates a plurality of equivalent signal point sequences in response to a digital data input. The signal point sequences are analyzed and compared relative to a predetermined cost metric such as transmit power. A preferred signal point sequence is selected and transmitted to the central site modem.

Abstract: The traditional association rule problem is extended by allowing a weight to be associate with each item in a transaction to reflect interest/intensity of each item within the transaction. The weighted association rules from a set of tuple lists are discovered, where each tuple consists of an item and an associated weight and each tuple list consists multiple tuples. The weighted association rules (WARs) are generated where some subset of items forms the consequent part of the rule (i.e., right hand side of the rule) and some other (non-overlapped) subset of items from the antecedent part of the rule (i.e., left hand side of the rule).

Abstract: A correlation detecting apparatus is capable of securely detecting a M sequence code forming a reference for timing even when a plurality of signals with different amplitudes are time division multiplexed includes matched filter (82) for detecting a predetermined code from a received signal, an average amplitude detector circuit (83) for detecting an average amplitude of the received signal, and a divider circuit (84) for normalizing an output of the matched filter (82) by an output of the average amplitude detector circuit 83 are provided. The output of the matched filter (82) normalized by the divider circuit (84) is compared with a threshold value for outputting a correlation detecting signal. When a received signal level is large, the output level of the matched filter (82) becomes large.

Abstract: Disclosed is a PLL control method of controlling a phase of a PLL for taking synchronism of a receiving signal in a data receiving apparatus. The phase of the PLL is synchronized with a phase when training irrespective of a line characteristic.

Abstract: An apparatus and method for compensating audio signals to be recorded on an optical disc to optimize usage of memory in an audio decoding circuit, and to neutralize invalid audio data to produce good audio quality. A determination is made with regard to whether audio data signals contain normal data or invalid data. Invalid data is adjusted into normal audio data, and stored in the memory. The volume of the data stored in the memory is monitored to detect overflow and underflow conditions of the memory, a data transmitting stopping signal being sent during an overflow condition of the memory, a data transmitting requesting signal being sent during an underflow condition. The audio data reproduced from the memory is decoded, and the decoded audio data is output. Undesired errors are prevented by monitoring the reproduced audio data for invalid data and by adjusting invalid data into normal data when detected.

Abstract: An activation method for adaptive equalization in a data transceiver including a plurality of adaptive filters wherein the adaptive filters are adapted with a first type of adaptation method to obtain initial convergence of the adaptive filters during an initial activation of the data transceiver and a second type of adaptation method to optimize performance of recovering the received signals in the presence of noise.

Abstract: The present invention is a data detection channel with improved detection reliability and better immunity to signal dropout and noise, that has reduced data redundancy. The data detection channel includes a preamp/filter, a sample/quantizer, an equalizer, a timing recovery circuit and a digital detection filter. The digital detection filter includes a finite impulse response filter, a synchronization and windowing device and a data detection circuit. The a finite impulse response filter has a plurality of coefficients and stores a plurality of channel data samples. On each cycle of the sampling clock, the finite impulse response filter is operable to input and store a channel data sample and output a sum signal representing a sum of each product of each coefficient multiplied by a corresponding stored channel data sample. The synchronization and windowing device is operable to receive the sum signal each sampling clock cycle and output the sum signal, if it corresponds to a symbol.

Abstract: A digital phase synchronizing apparatus delays sequentially a clock signal output from an oscillator, generates a plurality of delayed clock signals, selects a delayed clock signal that is synchronized with horizontal synchronizing signal HS from among the delayed clock signals using a change point detection circuit, and selects the output signal. Meanwhile, fine delay circuit further delays sequentially the selected delayed clock signal, generates a plurality of delayed clock signals, and selects a delayed clock signal that corresponds to the setting of a rotary dip switch as the system clock, thereby to efficiently acquire phase synchronization of the clock signal with the input signal without being affected by the signal characteristics of the input signal.

Abstract: A method and apparatus improves transmission quality of transmission media in a punctuated noise environment by terminating transmission during duration of punctuated large noise changes and alters network parameters, of the transmission media, to accommodate changes in level of stable noise conditions between punctuated large noise changes. Each stable noise level encountered is measured and its characteristics (i.e., level) is stored in a data base and associated network parameters (i.e., bit rates, bandwidth etc.) are changed accordingly and used to control or maintain quality of the transmission media.

Abstract: The present invention relates to a method and apparatus for adaptively compensating for channel or system variations in which adaptive compensation is used in the receiver of a digital communication system. The transmitter of the digital communication system includes precoding. The adaptive receiver compensation mitigates the interferences not removed by the transmitter precoder. In an embodiment of the invention, the adaptive compensation can be performed using an adaptive feedforward filter (FFF) and a feedback filter (FBF) in the receiver. The FBF output is generated based on previous values of estimates of the transmitted precoded sequence. The determined value of the FBF coefficients can be periodically relayed to the transmitter to update the precoder coefficients of the transmitter. Alternatively, the value of the FBF coefficients can be relayed to the transmitter after the value of the coefficients exceeds a predetermined threshold.

Abstract: A &pgr;/4 DQPSK modulator includes a rotated and offset &pgr;/4 encoder that provides encoded I, Q constellation indices values using positive integers. The positive integer I and Q values are input to a digital filter that provides filtered I, Q constellation indices values. These filtered values are then rotated and offset back to conventional &pgr;/4 DQPSK constellation values, modulated and transmitted. Since the rotated and offset &pgr;/4 encoder provides I, Q constellation indices as positive integers, the filters are implemented as multiplierless digital filters which significantly reduces the complexity of the filters. Specifically, the multiplierless digital filters can be implemented using shift registers and summers. In a preferred embodiment the filters are programmable. In addition, using positive integers to represent the rotated and offset &pgr;/4 signalling constellation indices allows the indices to be represented as a binary value with less bits in contrast to prior art systems.

Abstract: The present invention provides a method and apparatus for synchronizing signal transfers between two clock domains, where the clock domains have a gear ratio relationship. A gear ratio means that the clocks are related by a ratio, such that each clock has a different integer number of clock cycles in a common period. Also, in addition to a gear ratio relationship, the clocks may have a synchronized edge at the end of the common period. For each clock, the cycles in the common period are “colored”, i.e., identified by a number (1st, 2nd, etc.). By using the coloring technique, the appropriate clock edge to perform a data or control signal transfer can be identified. The edges are preferably chosen to minimize the latency of the transfer.

Abstract: A state-holding circuit initializing circuit initializes state-holding circuit when propagation of forward pulse to the forward-pulse delay circuits in the last stage is detected. With this operation, synchronization is established in a short time from the resumption of outputting from a receiver. The state-holding circuit control circuit also controls the reset timing of the state-holding circuit. A forward-pulse adjusting circuit controls the pulse width of forward pulse to be supplied to the forward-pulse delay line. With this operation, the stages from the stage where rearward pulse was generated to the first stage are securely turned to the set state, enabling propagation of rearward pulse and synchronization is established. Thus, synchronization is established reliably even when output from a receiver stops or the duty of an external clock signal is heavy.

Abstract: A method of frequency offset estimation and correction for adaptive antennas comprises receiving in a processor samples of a data set having a training data sample sequence. A batch least squares weight solution is computed for the training data sample sequence to obtain a least square error for each sample. Each error sample is rotated by multiplying by the conjugate of a sample of the reference training sequence and each rotated error sample is numbered (in the order received). A straight line is fit to the imaginary part of the rotated error sample (as a function of sample number) to obtain a frequency offset estimate. Each sample in a time slot of the samples of a dataset is multiplied by a complex exponential function of the frequency offset estimate.

Abstract: The output from a digital signal amplitude regenerator circuit in which the amplitude of a transmitted burst data signal is amplified, and an initial potential generator circuit, are connected to a switch. While there are no burst data, the initial potential generator circuit provides a circuit for compensating for degradation in pulse width comprising a low-pass filter, a pulse width compensation threshold generator circuit, and a limiting amplifier, with an initial potential needed to set a threshold. When a carrier detection signal generator circuit detects the arrival of a burst data signal, a carrier detection signal is outputted, and the switch is switched over from the initial potential to the burst data signal. Thus, the circuit for compensating for the degradation in pulse width located at a later stage can detect a threshold from an optimal initial potential, and thereby the degradation in pulse width can be optimally compensated.

Abstract: A system and method is provided having an adaptive channel coder and modulator, a channel decoder and demodulator connected to the adaptive channel coder and modulator, and a radio link protocol frame and channel decision unit connected to the adaptive channel coder and modulator.

Abstract: A circuit and method comprising a charge pump having a first and a second differential element. The charge pump may be configured to generate a first and a second output signal in response to the first and second differential elements. The first differential element may comprise (i) a first unity gain buffer and (ii) a first and a second transistor pair configured to receive a first and second control signal. The second differential element may comprise (i) a second unity gain buffer and (ii) a third and a fourth transistor pair configured to receive the first and second control signals. The first and second unity gain buffers may stabilize the source nodes of each of the transistors pairs.