Abstract: A test system for a evaluating a digital signal link includes a data signal generator, a data signal receiver, a digital signal link to be tested and a test interference signal injection (TISI) network connected as part of the digital signal link. The TISI network includes a data signal input port for receiving digital data signals generated by the data signal generator, a data signal output port for providing the digital data signals to the data signal receiver, and a controlled impedance data signal path carrying the digital data signals between the data signal input port and the data signal output port. An interference signal input port receives interference signals over a range of frequencies from an interference signal generator. One or more directional couplers directionally couple the interference signals into the data signal path toward either the data signal output port or the data signal input port at an impedance that substantially matches the impedance of the digital signal link.

Abstract: An apparatus for serial data communication between a plurality of IC chips with a reduced number of inter-chip signal lines. In the apparatus, one IC chip acts as a master, while the other chip(s) are slaved to it. In response to conditions internal to the master chip or in response to a request from at least one of the slave chips, the master chip generates a transfer control signal and a synchronization clock signal. The transfer control signal defines a transfer phase during which data transfer among the chips can take place. The chips take turns sending and receiving data in a multiplexed fashion. with sending and receiving parties designated by a count of synchronization clock signal cycles. The synchronization clock signal is generated at a high frequency, to allow fast data transfer.

Abstract: A Cartesian loop transmitter for transmitting baseband signals is disclosed. The disclosed Cartesian loop includes a forward path having a first input for receiving the baseband signals and a second input and a feedback path having an input from the forward path. The forward path including an upconverter to upconvert the input signals to a signal to be transmitted, an attenuator having selectable attenuation and a plurality of power amplifier stages. The feedback path including a pin diode attenuator having selectable attenuation and a downconverter to downconvert the input from the forward path. The feedback path provides an error signal indicative of the non-linearity of the forward path to the second input of the forward path.

Abstract: A mobile unit for communicating with a transmitter which transmits signals in data bursts, such data bursts having a plurality of symbols therein including data symbols and a plurality of predetermined pilot symbols. The symbols have a discrete number of possible values. The unit further includes a receiver adapted to receive a data burst of the transmitted signals, memory with the predetermined pilot symbols and a plurality of signal filters, a comparator, a processor, and an output. The comparator compares the pilot symbols in a received data burst with the predetermined pilot symbols in the memory to determine correction factors for the pilot symbols. The processor uses the pilot symbol correction factors and the plurality of signal filters to derive a set of data symbol correction factors for each of the signal filters.

Abstract: Delays in a spread spectrum signal transmitted in a communications medium according to a spreading sequence may be determined by receiving a composite signal including the spread spectrum signal from the communications medium. The composite signal is correlated with the spreading sequence according to a first correlation length, to produce first time-offset correlations of the composite signal with the spreading sequence. Selected ones of the first time-offset correlations of the composite signal then are further correlated with the spreading sequence according to a second correlation length that is longer than the first correlation length, to produce second time-offset correlations of the composite signal with the spreading sequence. At least one of the second time-offset correlations may be selected.

Abstract: A device for linearizing a transmitter in a digital radio communication system. In the device, a predistortion lookup table stores predistortion data determined by measuring in advance distortion characteristics of the transmitter with respect to input baseband data. During transmission, the device synthesizes the input baseband data with the predistortion data to predistort the input data so as to compensate for the distortion characteristics caused by non-linear elements constituting the transmitter.

Abstract: Burst transmissions in a burst-type communication system include a preamble synchronization sequence which allows detection and synchronization a burst transmission while at the same time providing information to a receiver, for example, on the subsequent burst payload data. Each burst transmission includes a preamble synchronization sequence which is one of a plurality of predetermined allowed preamble sequences in the system, according to the information desired to be transmitted. The system may also use differential encoding and decoding to eliminate the effects of frequency uncertainty. In that case, the allowed preamble sequences may be such that, after differential decoding, they differ from one another only by a polarity inversion such that a single matched filter may be used to detect two preamble sequences.

Abstract: In order to rapidly converge a gain control operation of an AGC amplifier which is provided for amplifying burst signals, a level of an incoming bust signal is detected. Following this, a signal indicative of the level of the burst signal is latched in response to a first latch control signal. On the other hand, an output of said AGC amplifier is derived and a level deviation thereof from a reference level is detected. Subsequently, a signal indicative of the level deviation is latched in response to a second latch control signal. The above-mentioned gain control signal is generated using the two kinds of signals held in the latches.

Abstract: A method and apparatus for performing fractional minimum shift key modulation for a very small aperture terminal. A signal with a fractional modulation which appears to be frequency shift key is generated in the indoor unit. The outdoor unit employs a novel multiplication method to translate this signal to a minimum shift key modulated signal for satellite transmission.

Abstract: The present invention relates generally to receivers in DS-CDMA receivers, and more particularly to the need for providing a pulse-matched filter to eliminate interchip interference. A CDMA RAKE receiver is used. Instead of applying a pulse-matched filter to the input signal as in state of the art systems, a one-bit pulse-matched filter is applied to the spreading sequence, preferably a pseudonoise (PN) sequence, which interpolates up to the required oversampling ratio. Since the filter has a one-bit input, the multipliers can be replaced by adders which consume less power. Also, the number of adders does not increase with the oversampling ratio as do the number of multipliers in the prior art.

Abstract: An automatic equalizer that can realize high-quality signal equalization without erroneous decision in the environment where a sequence candidate tends to be erroneously selected due to noises because the component corresponding to a demodulation point is close to the precursor component in magnitude. The automatic equalizer outputs the absolute values of impulse response signals, determines as candidate signals response absolute value signals larger than a threshold value, selects as a demodulation point a point corresponding to a candidate signal with the smallest propagation value among the candidate signals, and decides the selected point as a demodulation point setting signal.

Abstract: A constrained-envelope digital-communications transmitter circuit (22) includes a binary data source (32) that provides an input signal stream (34) to a modulator (77,77′). The modulator (77,77′) includes a pulse-spreading filter (76) that filters a phase-point signal stream (50) or a composite signal stream (168) into a modulated signal (74). A constrained-envelope generator (106) generates a constrained-bandwidth error signal stream (108) from the modulated signal (74), and a delay element (138) delays the modulated signal (74) into a delayed modulated signal (140) synchronized with the constrained-bandwidth error signal stream (108). A complex summing circuit (110) sums the delayed modulated signal (140) and the constrained-bandwidth error signal stream (108) into an altered modulated signal (112), and a substantially linear amplifier (146) amplifies the altered modulated signal (112) and transmits it as a radio-frequency broadcast signal (26).

Abstract: A circuit for controlling an equalization pulse width is disclosed that enables a stable data and minimizes or reduces a speed delay. The control circuit for the equalization pulse width includes a pulse generator for forming a predetermined pulse width in accordance with a set option when address signals are transited, and an addition unit for combining pulses formed by each of the address signals. A pulse latch unit continuously latches an equalization signal in an enabled state when signals are all enabled using a signal by which a redundancy Y-selection signal is enabled when a redundancy occurs in a coding signal from a Y-predecoder.

Abstract: An apparatus which can achieve a synchronous dubbing and can record new data at a position just after data previously recorded without an unnatural gap and without using a buffer memory with large capacity. A reference signal from a cylinder servo circuit/tape transport servo circuit of a transmitter is converted into an isochronous packet. The packet is sent out from a digital interface transmitting circuit to a 1394 cable. On the reception side, an isochronous packet converter circuit restores a received isochronous packet into an original reference signal and sends it to the cylinder servo circuit/tape transport servo circuit. By so doing, the transmitter and the receiver are synchronized with each other, and it becomes possible to achieve a synchronous dubbing and to record new data at a position just after data previously recorded without an unnatural gap. Then the transmitter sends out dubbing data and the receiver receives it.

Abstract: In a first embodiment of the invention, a concatenated preamble code is formed by a kronecker product between two subcodes of the same or different lengths. The subcodes have favorable correlation properties and may be Barker codes, minimum peak sidelobe codes, Gold codes, Kasami codes, Boztas codes, or other codes. At the receiver a two-stage processor is used to detect the concatenated preamble code. The two-stage processor comprises a series of two filters, one of which is preferably a mismatched filter. In another aspect of the invention, a repeated codeword preamble is formed from a series of the same repeated short subcode. The short subcode may be an augmented or truncated odd-length code. At the receiver a single matched filter is preferably used to generate a series of spikes separated by the period of the subcode. An alert/confirm detector non-coherently adds together individual correlation spikes and reject false alarms.

Abstract: A method and a timing recovery system for generating a set of clock signals in a system which includes a set of subsystems. Each of the subsystems includes an analog section. The set of clock signals includes a set of sampling clock signals. Each of the analog sections operates in accordance with a corresponding one of the sampling clock signals. For each of the sampling clock signals, a phase error is generated from a corresponding phase detector. The phase errors are filtered by a set of corresponding loop filters. The filtered phase errors are provided to a set of corresponding oscillators to generate phase control signals. The phase control signals are provided to a set of corresponding phase selectors to generate the sampling clock signals.

Abstract: A closed feedback loop controls the slicing, or detecting, of an incoming data signal. Detected signal information about the positive and negative peaks of the incoming data signal is processed to generate positive and negative peak reference signals which serve as reference signal levels for establishing the thresholds at which signal slicing takes place.

Abstract: Briefly, in accordance with one embodiment of the invention, a method of performing high speed signaling includes the following. A preamble signal and an end of packet (EOP) signal are transmitted at a low frequency using rail-to-rail voltage signal levels. Later, high frequency signaling is transmitted using a voltage signal level swing that is less than rail-to-rail.

Abstract: A system for transmitting information from a source to a destination using multilevel signaling. Multiple conductors are coupled between the transmission source and the transmission destination. Multiple drivers are coupled to the conductors at the transmission source. Each driver is coupled to a pair of conductors. Multiple comparators are coupled to the conductors at the transmission destination. Each comparator is coupled to a pair of conductors. The information is encoded into a sequence of symbols in which each symbol represents a unique permutation of signal levels on the conductors. Each signal level is used at least once for each symbol. All signal levels associated with a particular symbol are transmitted over the conductors simultaneously.

Abstract: Two input binary signals are sampled in preparation for being encoded into one signal. The encoded signal is provided with one of the three discrete states based on the sample binary states of the two input signals. A first discrete state is provided if the sampled binary state of the first input signal is a first of two binary states. A second discrete state is provided if the sampled binary state of the first input signal is a second of two binary states, and if two sampled binary states of the second input signal are the same. A third discrete state is provided if the sampled binary state of the first input signal is a second of two binary states, and of the two sampled binary states of the second input signal are different. A corresponding decoding method is also described.