Abstract: Described herein are techniques, systems, and circuits for addressing image data according to blocks. For example, in some cases, the address space may be divided into high order address bits and low order address bits. In these cases, an address circuit may twist an address space by shifting the high order bits and low order bits of an address in a rightward direction, shifting the low order bits of the address in a leftward direction, and shifting the high order bits and the low order bits of the address in the leftward direction. The circuit may modify the address value and untwist the address space. For example, the untwisting may include shifting the high order bits and the low order bits of an address in the rightward direction, shifting the low order bits of the address in the rightward direction, and shifting the high order bits and the low order bits of the address in the leftward direction.

Abstract: Various aspects provide for managing data associated with a cache memory. For example, a system can include a cache memory and a memory controller. The cache memory stores data. The memory controller maintains a history profile for the data stored in the cache memory. In an implementation, the memory controller includes a filter component, a tagging component and a data management component. The filter component determines whether the data is previously stored in the cache memory based on a filter associated with a probabilistic data structure. The tagging component tags the data as recurrent data in response to a determination by the filter component that the data is previously stored in the cache memory. The data management component retains the data in the cache memory in response to the tagging of the data as the recurrent data.

Abstract: Generating a virtual storage area network (VSAN) is disclosed. From the perspective of a customer's virtual machine, the VSAN is a logical network of storage devices that provide features that are typically associated with a physical storage access network, such as block level data storage; logical disk arrays; tape libraries; optical jukeboxes; quality of service; disk mirroring, backup and restoration services; archival and retrieval of archived data; data migration from one virtual storage device to another; sharing of data among different virtual machines in a network; and the incorporation of virtual subnetworks.

Abstract: Techniques described herein are generally related to retrieval of data in computer systems having multi-level caches. The multi-level cache may include at least a first cache and a second cache. The first cache may be configured to receive a request for a cache line. The request may be associated with an instruction executing on a tile of the computer system. A suppression status of the instruction may be determined by a first cache controller to determine whether look-up of the first cache is suppressed based upon the determined suppression status. The request for the cache line may be forwarded to the second cache by the first cache controller after the look-up of the first cache is suppressed.

Abstract: Methods and apparatus relating to techniques for Cross-Die Interface (CDI) snoop and/or go (or completion) message ordering are described. In one embodiment, the order of a snoop message and a completion message are determined based at least on status of two bits. The snoop and completion messages are exchanged between a first integrated circuit die and a second integrated circuit die. The first integrated circuit die and the second integrated circuit die are coupled through a first interface and a second interface and the snoop message and the completion message are exchanged over at least one of the first interface and the second interface. Other embodiments are also disclosed.

Abstract: Examples of the present disclosure provide apparatuses and methods for determining a data storage layout. An example apparatus comprising a first address space of a memory array comprising a first number of memory cells coupled to a plurality of sense lines and to a first select line. The first address space is configured to store a logical representation of a first portion of a value. The example apparatus also comprising a second address space of the memory array comprising a second number of memory cells coupled to the plurality of sense lines and to a second select line. The second address space is configured to store a logical representation of a second portion of the value. The example apparatus also comprising sensing circuitry configured to receive the first value and perform a logical operation using the value without performing a sense line address access.

Abstract: A dynamic content disk for a virtual computing instance is created as a thinly-provisioned virtual disk having a file system that is synthesized in accordance with a set of applications that are provisioned for a virtual machine (VM). To limit the allocated size of the dynamic content disk, a filter is attached to the dynamic content disk to intercept input-output operations (IOs) directed to the dynamic content disk and convert them to IOs directed to an application virtual disk that stores the actual files of the applications that are provisioned for the VM. The application virtual disk may be stored on different back-ends, such as storage area network (SAN), network file system, virtual SAN, cloud storage, or local storage.

Abstract: The embodiments of the invention describe settings, commands, command signals, flags, attributes, parameters or the like for signed access prior to allowing data to be written to (e.g., a write access), read from (e.g., a read access) or erased from (e.g., an erase access) protected areas of a memory device (e.g., a region, logical unit, or a portion of memory in the storage module).

Abstract: A translation-lookaside buffer (TLB) includes a plurality of entries, wherein each entry of the plurality of entries is configured to hold an address translation and a local valid bit vector, wherein each bit of the local valid bit vector is mapped from a different value of an x86 instruction set architecture (ISA) process context identifier (PCID). The TLB also includes an input that receives an invalidation bit vector having bits corresponding to the bits of the local valid bit vector of the plurality of entries. The TLB also includes logic that simultaneously invalidates a bit of the local valid bit vector of each entry of the plurality of entries that corresponds to a set bit of the invalidation bit vector.

Abstract: In an embodiment of the invention, an apparatus comprises: a hard disk drive input/output (HDD I/O) optimizer configured to receive a primary input/output (I/O) operation stream for a given cylinder in a permanent storage device, configured to schedule a secondary input/output (I/O) operation stream that is pending on the same given cylinder or that is pending on an adjacent cylinder that is adjacent to the given cylinder, and configured to allocate free space from the same given cylinder or from the adjacent cylinder for the secondary I/O operation stream that is pending.

Abstract: Methods and apparatuses to control cache line coherence are described. A hardware processor may include a first processor core with a cache to store a cache line, a second set of processor cores that each include a cache to store a copy of the cache line, and cache coherence logic to aggregate in a tag directory an acknowledgment message from each of the second set of processor cores in response to a request from the first processor core to modify the copy of the cache line in each of the second set of processor cores and send a consolidated acknowledgment message to the first processor core.

Abstract: A workload level associated with an expandable data buffer is determined, where the expandable data buffer and an expandable mapping table cache are stored in internal memory and the expandable mapping table cache is used to store a portion of a mapping table that is stored on external storage. An amount of internal memory allocated to the expandable data buffer and an amount of internal memory allocated to the expandable mapping table cache are adjusted based at least in part on the workload level.

Abstract: Embodiments of the present invention disclose a method and apparatus of cache management for a non-volatile storage device. The method embodiment includes: determining a size relationship between a capacity sum of a clean page subpool and a dirty page subpool and a cache capacity; determining, when the capacity sum is equal to the cache capacity, whether identification information of a to-be-accessed page is in a history list of clean pages or a history list of dirty pages; and when it is determined that the identification information of the to-be-accessed page is in the history list of clean pages, adding a first adjustment value to a clean page subpool capacity threshold; and when the identification information of the to-be-accessed page is in the history list of dirty pages, subtracting a second adjustment value from the clean page subpool capacity threshold.

Abstract: A method and associated systems for efficient management of cloned data. One or more processors create a “child” clone of a “parent” software image. The child and parent contain identical information organized into identical sets of file blocks. To conserve storage, each child block initially points to a physical storage location already in use by a corresponding parent block, rather than requiring additional storage of its own. The first time a child block is updated, however, it will require additional physical storage. At the time of the child's creation, the processors reserve a number of physical blocks sufficient to store the contents of all child file blocks likely to be updated. A child file block is identified as likely to be updated by analyzing past volatility of a corresponding file block of the parent or of corresponding file blocks of other children of the same parent.

Abstract: In semiconductor devices with nonvolatile memory modules embedded therein, a technology is provided which facilitates evaluation of the nonvolatile memory characteristics. An MCU includes a CPU, a flash memory, and an FPCC that controls write or erase operations to the flash memory. The FPCC executes a program used to perform write or other operations to the flash memory, thereby performing write or other operations to the flash memory in accordance with a command issued by the CPU. In the MCU, the FCU is configured to execute test firmware to evaluate the flash memory. In addition, a RAM can be used by both the CPU and FCU.

Abstract: For reducing lock contention on a Modified Least Recently Used (MLRU) list for metadata tracks, upon a conclusion of an access of a metadata track, if one of the metadata track is located in a predefined lower percentile of the MLRU list, and the metadata track has been accessed, including the access, a predetermined number of times, the metadata track is removed from a current position in the MLRU list and moved to a Most Recently Used (MRU) end of the MLRU list.

Abstract: A memory system and a method of operating the same are provided. The method includes storing a first map table including a mapping relation between first physical addresses specifying pages of memory blocks having multi-level cells and first logical addresses, storing first logical address groups of the first logical addresses as meta information, determining a second logical address group of a request address, detecting whether the second logical address group is in the first logical address groups of the meta information, and searching for the request address in the first map table based on the detecting result.

Abstract: Embodiments of the invention relate to tracking processor transactional read and write sets, thereby eliminating speculative mis-predictions. Both non-speculative read set and write set indications are maintained for a transaction. The indications are stored in cache. In addition, load and write queues of addresses are maintained. The load queue of addresses relates to speculative members of a read set and the write queue of addresses relates to speculating member of a write set. For a received read request, a transaction resolution process takes place, and a resolution is performed if an address match in the write queue is detected. Similarly, for a receive write request the transaction interference additionally checks the load queue and the non-speculative read set for the pending address.

Abstract: Machine implemented method and system for generating a disaster recovery copy of an expandable storage volume having a namespace for storing information for accessing data objects stored at a data constituent volume is provided. A transfer operation for transferring a point in time copy of the expandable storage volume from a first location to a second location is generated. Information regarding the expandable storage volume from the first location is retrieved and a destination expandable storage volume is resized to match components of the expandable storage volume at the first location. Thereafter, the point in time copy of the expandable storage volume from the first location to the second location is transferred and configuration information regarding the point in time copy is copied from the first location to the second location; a data structure for storing information regarding the transferred point in time copy of the expandable storage volume is updated.

Abstract: Computerized methods and systems for automating a process of creating and mounting live copies of data to applications in accordance with workflows that specify procedures for creating and mounting the live copies of data to the applications. The methods and systems comprise executing at least one workflow associated with a data object based on a triggering event, and executing a set of configurable work actions associated with the at least one workflow; creating a snapshot of data volumes associated with the data object; creating liveclone volumes based on the snapshot of the data volumes, and mounting and dismounting the liveclone volumes to and from at least one application.