Patents Examined by Jean Edouard
  • Patent number: 9081607
    Abstract: A method for executing a transaction in a data processing system initiates the transaction by a transactional-memory system coupled to that memory component. The method includes initiating the transaction by a transactional-memory system that is part of a memory component of the data processing system. The transaction includes instructions for comparing multiple parameters, and aborting the transaction by the transactional-memory system based upon a comparison of the multiple parameters.
    Type: Grant
    Filed: October 24, 2012
    Date of Patent: July 14, 2015
    Assignee: International Business Machines Corporation
    Inventors: Robert J Blainey, Harold W Cain, III, Bradly G Frey, Hung Q Le, Cathy May
  • Patent number: 9075721
    Abstract: A program for causing an information processing apparatus to execute a process of a virtual calculator, the process including judging, when a switching of a virtual address space being a processing target of a virtual calculation apparatus occurs, whether or not a there exits physical calculation apparatus in which cache information of a physical address space corresponding to a virtual address space of a switching destination is accumulated; selecting the physical calculation apparatus when there exists a physical calculation apparatus in which the cache information of the physical address space is accumulated, and selecting the physical calculation apparatus in which cache information itself is not accumulated when there exists no physical calculation apparatus in which the cache information is accumulated; and assigning the selected physical calculation apparatus to the virtual calculation apparatus in which the switching of the virtual address space being a processing target has occurred.
    Type: Grant
    Filed: February 25, 2013
    Date of Patent: July 7, 2015
    Assignee: FUJITSU LIMITED
    Inventor: Hidetaka Tamura
  • Patent number: 9069710
    Abstract: Machine implemented method for generating and accessing a point in time copy of an expandable storage volume in a network storage system is provided. The expandable storage volume includes a namespace for storing information for accessing data objects stored at a plurality of data constituent volumes managed by a plurality of nodes of the storage system. The method includes initiating a logical fence first for the namespace and then for the data constituent volumes for generating the point in time copy of the expandable storage volume. The logical fence filters out any information written after the fence is initiated from the point in time copy of the expandable storage volume.
    Type: Grant
    Filed: March 28, 2012
    Date of Patent: June 30, 2015
    Assignee: NETAPP, INC.
    Inventors: Kiran K. Modukuri, Logan R. Jennings
  • Patent number: 9043560
    Abstract: Systems, methods, and other embodiments associated with a distributed cache coherency protocol are described. According to one embodiment, a method includes receiving a request from a requester for access to one or more memory blocks in a block storage device that is shared by at least two physical computing machines and determining if a caching right to any of the one or more memory blocks has been granted to a different requester. If the caching right has not been granted to the different requester, access is granted to the one or more memory blocks to the requester.
    Type: Grant
    Filed: September 23, 2011
    Date of Patent: May 26, 2015
    Assignee: Toshiba Corporation
    Inventor: Arvind Pruthi
  • Patent number: 9043567
    Abstract: Machine implemented method and system for generating a disaster recovery copy of an expandable storage volume having a namespace for storing information for accessing data objects stored at a data constituent volume is provided. A transfer operation for transferring a point in time copy of the expandable storage volume from a first location to a second location is generated. Information regarding the expandable storage volume from the first location is retrieved and a destination expandable storage volume is resized to match components of the expandable storage volume at the first location. Thereafter, the point in time copy of the expandable storage volume is transferred from the first location to the second location and configuration information regarding the point in time copy is copied from the first location to the second location.
    Type: Grant
    Filed: March 28, 2012
    Date of Patent: May 26, 2015
    Assignee: NETAPP, INC.
    Inventors: Kiran K. Modukuri, Logan R. Jennings
  • Patent number: 9026757
    Abstract: A system and methods for programming a set of data onto non-volatile memory elements, maintaining copies of the data pages to be programmed, as well as surrounding data pages, internally or externally to the memory circuit, verifying programming correctness after programming, and upon discovering programming error, recovering the safe copies of the corrupted data to be reprogrammed in alternative non-volatile memory elements. Additionally, a system and methods for programming one or more sets of data across multiple die of a non-volatile memory system, combining data pages across the multiple die by means such as the XOR operation prior to programming the one or more sets of data, employing various methods to determine the correctness of programming, and upon identifying data corruption, recovering safe copies of data pages by means such as XOR operation to reprogram the pages in an alternate location on the non-volatile memory system.
    Type: Grant
    Filed: January 25, 2013
    Date of Patent: May 5, 2015
    Assignee: SanDisk Technologies Inc.
    Inventor: Yan Li
  • Patent number: 8990522
    Abstract: A technique for transferring data in a digital signal processing system is described. In one example, the digital signal processing system comprises a number of fixed function accelerators, each connected to a memory access controller and each configured to read data from a memory device, perform one or more operations on the data, and write data to the memory device. To avoid hardwiring the fixed function accelerators together, and to provide a configurable digital signal processing system, a multi-threaded processor controls the transfer of data between the fixed function accelerators and the memory. Each processor thread is allocated to a memory access channel, and the threads are configured to detect an occurrence of an event and, responsive to this, control the memory access controller to enable a selected fixed function accelerator to read data from or write data to the memory device via its memory access channel.
    Type: Grant
    Filed: October 5, 2012
    Date of Patent: March 24, 2015
    Assignee: Imagination Technologies Limited
    Inventors: Adrian J. Anderson, Gary C. Wass, Gareth J. Davies
  • Patent number: 8943270
    Abstract: In tiered storage subsystems in which pages are automatically allocated to appropriate storage media based on the access frequency in page units, since the number of storage media is not simply proportional to the performance, it was difficult to design in advance a tier configuration satisfying the required performance. According to the present invention, a cumulative curve of I/O distribution is created based on a result of measurement of I/O accesses performed to the storage subsystem, and RAID groups (RG) are allocated sequentially in order from RGs belonging to tiers having higher performances to the cumulative curve of I/O distribution. When either a performance limitation value or a capacity of the RG exceeds the cumulative curve of I/O distribution, a subsequent RG is allocated, and the process is repeated so as to compute the optimum tier configuration.
    Type: Grant
    Filed: July 24, 2012
    Date of Patent: January 27, 2015
    Assignee: Hitachi, Ltd.
    Inventors: Hideki Nagasaki, Hirokazu Ogasawara, Taro Ishizaki