Abstract: A semiconductor storage device includes memory cells, select transistors, memory strings, a block, word lines, and select gate lines. In the memory string, the current paths of plural memory cells are connected in series. When data are written in the block, after a word line connected to the control gates of memory cells of different memory strings in the second block is selected, the data are sequentially written in the memory cells of the different memory strings in the block which have their control gates connected to the selected word line.

Abstract: Storage system: wherein processor number information includes at least one logical unit number and at least one processor number of storage nodes; wherein transfer list index/processor number information includes a processor number for identifying a processor from among processors of the plurality of storage nodes, and index information for identifying a transfer list including instruction which the processor sends to the protocol processor; wherein a local router determines a first processor from among the processors of the plurality of storage nodes which is to be a transfer destination of a write request based on processor number information in response to the write request from the host computer through the protocol processor; wherein the first processor generates and sends to the protocol processor a first transfer list which includes instruction for processing, and generates first index information which is an index of the first transfer list upon receiving the write request.

Abstract: A computer-implemented method can include receiving a set of software instructions for execution by a computing device and compiling the set of software instructions to generate a set of executable instructions. The compiling can include identifying a first memory object allocation instruction. The method can also include executing the set of executable instructions, where the executing includes allocating, in a young garbage collection generation, a plurality of memory objects with the first memory object allocation instruction. The method can further include determining a survival rate of the plurality of memory objects allocated by the first memory object allocation instruction.

Abstract: A data access system includes a storage device, an instruction management device, and a host device. The host device is configured to transmit an access instruction associated with an access operation directed to an intended physical address of the storage device to the instruction management device, which compares the access instruction with a specified instruction list. When the instruction management device determines that the access instruction conforms with an instruction included in the specified instruction list, the instruction management device is configured to generate a modified access instruction associated with an access operation directed to a target physical address that is different from the intended physical address of the storage device.

Abstract: A cache controller controls data input/output of the storage device and causes the semiconductor storage device to function as a cache memory of the storage device. A staging controller performs, when data is staged from the storage device to the cache memory, first staging amount control until a staging amount to the cache memory exceeds a first threshold after the storage apparatus starts up; performs second staging amount control until a variation per unit time of a read amount from the cache memory falls within a predetermined range after the first period; and performs third staging amount control after the second period. With this configuration, the semiconductor apparatus can be efficiently used.

Abstract: A CM 10 includes an unmount detector 142 and a mount detector 144 that monitor unmount and mount of each disk 21 of a RAID configuration, a write request manager 143 that manages a write request for writing data to a disk 21 that is unmounted, a consistency determination unit 145 that, when mount of a disk 21 of the RAID configuration is detected, makes a determination on consistency of the data of the disk 21 in which mount is detected on the basis of the managed write request, and a RAID incorporating unit that, when it is determined that the data lacks consistency, performs processing for recovering data expected to be written by the write request issued to the disk 21 in which mount is detected while the disk 21 is unmounted and incorporates the disk 21 in an original RAID configuration.

Abstract: An apparatus for managing a memory including a working region and a compression region is provided. The working region stores uncompressed data. The apparatus includes a management module and a compression/decompression module. According to a recent used index and a compression ratio of a set of target data stored in the working region, the management module determines whether to transfer the target data to the compression region. When the management module determines to transfer the target data to the compression region, the compression/decompression module compresses the target data and transfers the compressed target data to the compression region.

Abstract: Described herein are techniques, systems, and circuits for addressing image data according to blocks. For example, in some cases, the address space may be divided into high order address bits and low order address bits. In these cases, an address circuit may twist an address space by shifting the high order bits and low order bits of an address in a rightward direction, shifting the low order bits of the address in a leftward direction, and shifting the high order bits and the low order bits of the address in the leftward direction. The circuit may modify the address value and untwist the address space. For example, the untwisting may include shifting the high order bits and the low order bits of an address in the rightward direction, shifting the low order bits of the address in the rightward direction, and shifting the high order bits and the low order bits of the address in the leftward direction.

Abstract: Embodiments of the present invention provide a method and an apparatus for constructing a memory access model, and relate to the field of computers. The method includes: obtaining a page table corresponding to a process referencing a memory block, and clearing a Present bit included in each page table entry stored in the page table; and constructing a memory access model of the memory block according to the number of access times of each page in the memory block and time obtained through timing, where the memory access model at least includes the number of access times and an access frequency of each page in the memory block. The apparatus includes: a first obtaining module, a first monitoring module, a first increasing module, and a second obtaining module. The present invention can reduce the memory consumption and an impact on the system performance, and avoid a system breakdown.

Abstract: The present disclosure includes apparatuses and methods for command queuing. A number of embodiments include receiving a queued command request at a memory system from a host, sending a command response from the memory system to the host that indicates the memory system is ready to receive a command in a command queue of the memory system, and receiving, in response to sending the command response, a command descriptor block for the command at the memory system from the host.

Abstract: Communication between a host and a data storage device (DSD) including a first media for storing data and a second media for storing data. In one embodiment, a first controller of the DSD is configured to control operation of the first media and a second controller of the DSD is configured to control operation of the second media. The first controller receives a key data block of a monitoring system from the host with the key data block including a task file. The key data block is evaluated to determine if the key data block is directed to the second media, and if it is determined that the key data block is directed to the second media, the task file of the key data block is sent from the first controller to the second controller.

Abstract: Systems and methods are described for logical partitioning of library resources (e.g., storage media resources and/or media drive resources in storage libraries) across a complex of multiple, physically distinct, but logically interconnected data storage libraries. For example, a user selects complex-wide resources to add to one or more library partitions via a graphical user interface displayed on a local console of one of the storage library systems. The partitions can be validated and converted into a partition definition. In some implementations, the partition definition is redundantly stored as a predefined short format in local storage of some or all the storage library systems in the complex. This can minimize the resources used to store the partition definition, provide redundancy for added configuration options and/or in case of certain failures, speed up processing of resource queries, and/or provide other features.

Abstract: A memory system, a semiconductor memory device and methods of operating the same may perform a read operation on the basis of flag data stored in a flag register, without reading the flag data stored in a memory array, when performing the read operation, so that a time taken for the read operation may be reduced.

Abstract: A method and apparatus for capturing a snapshot of storage volumes of a data capture group are disclosed. In the method and apparatus, a request to create a data capture group may be received and processed. The data capture group may have one or more storage volumes. Upon defining the data capture group, a snapshot of the storage volumes of the data capture group may be taken.

Abstract: In accordance with embodiments disclosed herein, there are provided methods, systems, mechanisms, techniques, and apparatuses for cutting senior store latency using store prefetching. For example, in one embodiment, such means may include an integrated circuit or an out of order processor means that processes out of order instructions and enforces in-order requirements for a cache. Such an integrated circuit or out of order processor means further includes means for receiving a store instruction; means for performing address generation and translation for the store instruction to calculate a physical address of the memory to be accessed by the store instruction; and means for executing a pre-fetch for a cache line based on the store instruction and the calculated physical address before the store instruction retires.

Abstract: The present disclosure provides techniques for cache management. A data block may be received from an IO interface. After receiving the data block, the occupancy level of a cache memory may be determined. The data block may be directed to a main memory if the occupancy level exceeds a threshold. The data block may be directed to a cache memory if the occupancy level is below a threshold.

Abstract: Generally, this disclosure provides systems, devices, methods and computer readable media for memory object reference count management with improved scalability based on transactional reference count elision. The device may include a hardware transactional memory processor configured to maintain a read-set associated with a transaction and to abort the transaction in response to a modification of contents of the read-set by an entity external to the transaction; and a code module configured to: enter the transaction; locate the memory object; read the reference count associated with the memory object, such that the reference count is added to the read-set associated with the transaction; access the memory object; and commit the transaction.

Abstract: Techniques for reclaiming storage space are disclosed herein. According to one embodiment, a storage space reclamation method includes a storage host creating at least one temporary logical container of data in a storage volume managed by a file system of a host so that a predetermined portion of storage capacity of the storage volume is occupied. Access to the storage volume is provided by a network storage controller to the storage host. The storage host translates a host address range for the file system of each temporary logical container of data into a storage controller address range for the network storage controller. The storage host requests the network storage controller to deallocate blocks the locations of which are indicated by the storage controller address range, and then deletes the at least one temporary logical container of data.

Abstract: Implementation manners of the present invention provide a data storage method and apparatus. A fixed-length key and a value thereof are stored into a first data block, where the storing a fixed-length key includes: uniformly storing a common prefix of each fixed-length key, and separately storing a remainder part of each fixed-length key after the common prefix is removed; and a variable-length key and a length thereof are stored into a second data block, where the storing a variable-length key includes: storing a variable-length key of a base-key type in a full storage manner, and performing prefix compression on a variable-length key of a prefix-compressed key type.

Abstract: A data processing system includes a cache memory 58 and cache control circuitry 56 for applying a cache replacement policy based upon a retention priority value PV stored with each cache line 66 within the cache memory 58. The initial retention priority value set upon inserting a cache line 66 into the cache memory 58 is dependent upon either or both of which of a plurality of sources issued the access memory request that resulted in the insertion or the privilege level of the memory access request resulting in the insertion. The initial retention priority level of cache lines resulting from instruction fetches may be set differently from cache lines resulting from data accesses.