Abstract: A memory device having a primary memory element, in which the memory device includes an evaluation device to ascertain whether the primary memory element experiences a state change and to activate a secondary memory element so that if (a) the primary memory element experiences a state change, the secondary memory element does not carry out a state change, and if (b) the primary memory element does not experience a state change, the secondary memory element carries out a state change.

Abstract: A plurality of storage apparatuses including a first and second storage apparatus, wherein said first storage apparatus is configured to have a first virtual volume composed of a plurality of virtual segments, at least said second storage apparatus is configured to have a pool composed of a plurality of real pages, each storage apparatus is configured to manage a virtual pool comprising one or more pools including at least said pool, said virtual pool is composed of a plurality of virtual pages, each virtual page corresponding to any real page, and said first storage apparatus is configured to receive a write command that specifies an address belonging to an unallocated virtual segment, allocate a free virtual page to said unallocated virtual segment, and write data to the real page corresponding to the allocated virtual page, even when said first storage apparatus does not have a pool composed of real pages.

Abstract: An address translation capability is provided in which translation structures of different types are used to translate memory addresses from one format to another format. Multiple translation structure formats (e.g., multiple page table formats, such as hash page tables and hierarchical page tables) are concurrently supported in a system configuration. This facilitates provision of guest access in virtualized operating systems, and/or the mixing of translation formats to better match the data access patterns being translated.

Abstract: An electronic apparatus may be provided that includes a processor to perform operations, and a memory subsystem including a plurality of parallel memory banks to store a two-dimensional (2D) array of data using a shifted scheme. Each memory bank may include at least two elements per bank word.

Abstract: In one embodiment, the present invention includes a method for identifying a memory request corresponding to a load instruction as a critical transaction if an instruction pointer of the load instruction is present in a critical instruction table associated with a processor core, sending the memory request to a system agent of the processor with a critical indicator to identify the memory request as a critical transaction, and prioritizing the memory request ahead of other pending transactions responsive to the critical indicator. Other embodiments are described and claimed.

Abstract: A memory system has a storage unit having two or more parallel read/write processing elements and non-volatile data recording areas for a logical block divided into a plurality of logical pages, and a control unit that generates log information for each unit of data written into the recording areas, determines for each logical page a log information recording area from a group of recording areas of the logical page, and controls the parallel operation elements to write the log information generated for a logical page into the log information recording area of the logical page and the data of the logical page into the other recording areas of the group of recording areas of the logical page.

Abstract: An address translation capability is provided in which translation structures of different types are used to translate memory addresses from one format to another format. Multiple translation structure formats (e.g., multiple page table formats, such as hash page tables and hierarchical page tables) are concurrently supported in a system configuration. This facilitates provision of guest access in virtualized operating systems, and/or the mixing of translation formats to better match the data access patterns being translated.

Abstract: A refresh address generator includes a refresh sequence buffer and a refresh address generating unit. The refresh sequence buffer stores a sequence of memory groups, each memory group including a plurality of memory cell rows. The refresh address generating unit generates a plurality of refresh row addresses according to the sequence of memory groups stored in the refresh sequence buffer, in response to a refresh signal.

Abstract: Disclosed herein are system, method, and computer program product embodiments for storing and accessing data in a shared disk database system using a timestamp range to improve cache efficiency. An embodiment operates by retrieving, by a node, from a shared storage. a blockmap identity and a root page associated with a data request, based on a determination that the blockmap identity associated with a data request is present in a cache. The embodiment continues, retrieving, by the node, the logical page by copying a stored logical page from the shared storage and setting a lower timestamp value of the logical page to a timestamp associated with the stored logical page and an upper timestamp value of the logical page to a timestamp associated with the data request, based on a determination that the logical page is not present in the cache.

Abstract: The present idea provides a high read and write performance from/to a solid state memory device. The main memory of the controller is not blocked by a complete address mapping table covering the entire memory device. Instead such table is stored in the memory device itself, and only selected portions of address mapping information are buffered in the main memory in a read cache and a write cache. A separation of the read cache from the write cache enables an address mapping entry being evictable from the read cache without the need to update the related flash memory page storing such entry in the flash memory device. By this design, the read cache may advantageously be stored on a DRAM even without power down protection, while the write cache may preferably be implemented in nonvolatile or other fail-safe memory. This leads to a reduction of the overall provisioning of nonvolatile or fail-safe memory and to an improved scalability and performance.

Abstract: A method for memory management is provided for a memory including a plurality of pages. The method comprises assigning in-use pages to in-use buckets according to use counts. The in-use buckets include a low in-use bucket for a lowest range of use counts, and a high in-use bucket for a highest range of use counts. The method comprises assigning free pages to free buckets according to use counts. The free buckets include a low free bucket for a lowest range of use counts, and a high free bucket for a highest range of use counts. The method maintains use counts for in-use pages. On a triggering event for a current in-use page, the method determines whether the use count of the current in-use page exceeds a hot swap threshold, and if so moves data in the current in-use page to a lead page in the low free bucket.

Abstract: A virtual machine system comprises: a processor for executing a secure operating system and a normal operating system; and a cache memory. The cache memory stores data in a manner that allows for identification of whether the data has been read from a secure storage area of an external main memory. The cache memory writes back data to the main memory in a manner that reduces the number of times data is intermittently written back to the secure storage area which occurs when the processor is executing the normal operating system.

Abstract: An information recording device includes a recording medium in which renewal data, which is a target of a data refresh operation, is recorded, a reading module that reads the renewal data recorded in the recording medium, a renewal module that performs updating of a value indicating a state of the data refresh operation, a generation module that generates parity data based on the value and the read renewal data, and a recording module that records the renewal data after recording the generated parity data.

Abstract: A method of operation of a storage control system includes: calculating a throttle threshold; identifying a detection point based on the throttle threshold; and calculating a number of write/erase cycles based on the detection point and the throttle threshold for writing a memory device.

Abstract: Machine implemented method and system for generating a disaster recovery copy of an expandable storage volume having a namespace for storing information for accessing data objects stored at a data constituent volume is provided. A transfer operation for transferring a point in time copy of the expandable storage volume from a first location to a second location is generated. Information regarding the expandable storage volume from the first location is retrieved and a destination expandable storage volume is resized to match components of the expandable storage volume at the first location. Thereafter, the point in time copy of the expandable storage volume from the first location to the second location is transferred and configuration information regarding the point in time copy is copied from the first location to the second location; a data structure for storing information regarding the transferred point in time copy of the expandable storage volume is updated.

Abstract: A method for managing objects stored in a cache memory of a processing unit. The cache memory includes a set of entries corresponding to an object. The method includes: checking, for each entry of at least a subset of entries of the set of entries of the cache memory, whether an object corresponding to each entry includes one or more references to one or more other objects stored in the cache memory and storing the references; determining among the objects stored in the cache memory, which objects are not referenced by other objects, based on the stored references; marking entries as checked to distinguish entries corresponding to objects determined as being not referenced from other entries of the checked entries, and casting out, according to the marking, entries corresponding to objects determined as being not referenced.

Abstract: A semiconductor storage device includes memory cells, select transistors, memory strings, first and second blocks, word lines, and select gate lines. In the memory string, the current paths of plural memory cells are connected in series. When data are written in a first block, after a select gate line connected to the gate of a select transistor of one of the memory strings in the first block is selected, the data are sequentially written in the memory cells in the memory string connected to the selected select gate line. When data are written in the second block, after a word line connected to the control gates of memory cells of different memory strings in the second block is selected, the data are sequentially written in the memory cells of the different memory strings in the second block which have their control gates connected to the selected word line.

Abstract: The present invention pertains to a multi-profile memory controller and devices that use multi-profile memory controllers. More particularly, the present invention pertains to a multi-profile memory controller and related methods and systems that can operate with memory locations, memory devices, or both which are associated with different memory attributes, different attribute qualifiers, or the like, while minimizing or avoiding some or all of the disadvantages of the prior art.

Abstract: A plurality of storage apparatuses including a first and second storage apparatus, wherein said first storage apparatus is configured to have a first virtual volume composed of a plurality of virtual segments, at least said second storage apparatus is configured to have a pool composed of a plurality of real pages, each storage apparatuses is configured to manage a virtual pool comprising one or more pools including at least said pool, said virtual pool is composed of a plurality of virtual pages, each virtual page corresponding to any real page, and said first storage apparatus is configured to receive a write command that specifies an address belonging to an unallocated virtual segment, allocate a free virtual page to said unallocated virtual segment, and write data to the real page corresponding to the allocated virtual page, even when said first storage apparatus does not have a pool composed of real pages.

Abstract: An image reading apparatus includes an image data compression unit, an attribute data compression unit, and a memory. Of image data and attribute data generated by image reading, the image data compression unit compresses the image data. The attribute data compression unit compresses the attribute data. In the memory, a page memory region for storing the image data compressed by the image data compression unit and the attribute data compressed by the attribute data compression unit is secured. And, one of the compressed image data and the compressed attribute data is successively written from the beginning of the page memory region toward the end thereof, while the other of the compressed image data and the compressed attribute data is successively written from the end of the page memory region toward the beginning thereof.