Abstract: A computer system comprising a first expansion bus which operates according to a first transfer protocol and is adapted to couple to one or more peripheral devices. A central processing unit and a bus bridge are operatively coupled to the first expansion bus. A second bus including a second transfer protocol is coupled to the bus bridge. At least one peripheral device of a first type compatible with the second transfer protocol is coupled to the second bus. At least one peripheral device of a second type coupled to the second bus, wherein the at least one peripheral device of the second type is compatible with a third transfer protocol of a peripheral bus standard, the third transfer protocol of the peripheral bus standard being different from the second transfer protocol of the second bus. The bus bridge is operable to convert signals between the first expansion bus and the second bus, and is operable to implement the second transfer protocol on the second bus.

Abstract: A sleep mode controller, useful for an electronic device such as a computer, can supply multiple clocks with appropriate synchronization and which is capable of dynamic speed switching. The device provides clock signals at various speeds and relationships which can in turn be used to support various functions of the electronic device. The sleep mode controller can be activated and smoothly transition various clock signals from one time domain to a second time domain, each of which has predetermined speeds and clock-signal relationships. Dynamic speed switching is used to reset timing (bus and processor clock) sensitive elements such that computer machine speed (bus and processor clock frequencies) can be changed dynamically without interruption of I/O services or general OS and application level functions.

Abstract: A computer system having an interconnection apparatus for connecting processors, peripherals and memories, the system including a plurality of electronic devices, and a multiple long bus structure with impedance elements disposed thereon for providing non-terminal termination points.

Abstract: A method for generating an interrupt to a plurality of peripheral devices in a computer system, the computer system comprising a first bus, a bus bridge for coupling to the first bus and for interfacing to a second bus, a second bus coupled to the bus bridge, and a plurality of peripheral devices connected to the second bus. The method comprises activating a source port in the bus bridge to configure the source port in the bus bridge for a transfer. The bus bridge receives from the first bus and stores an encoded interrupt vector in a register of the source port. The encoded interrupt vector is indicative of one or more interrupt requests at a target peripheral device. The bus bridge transmits an address/data pair to a destination port of the target peripheral device. The address/data pair includes an address of the destination port and encoded interrupt vector received from the first bus.

Abstract: An interface between first and second data buses includes a first bus state machine which controls data transfers from the first data bus to a data buffer. The interface includes a second bus state machine which controls data transfers from the data buffer to the second data bus. The data buffer includes a plurality of storage locations accessed on a first-in/first-out basis. A respective valid data flag for each storage location is set by the first bus state machine when data are stored in the storage location from the first data bus and is cleared by the second bus state machine when data are transferred from the storage location to the second data bus. The data valid flags are synchronized with first and second bus clocks respectively associated with the first and second bus state machines to assure that the data valid flags change synchronously with respect to each state machine.

Abstract: A method and apparatus for extending a PCI bus interface to a remote I/O backplane through a high speed serial link, providing a large number of I/O slots to alleviate packaging requirements. The apparatus includes a local and a remote serial bridge coupled by a serial link, which is used to transceive messages. Each serial bridge may reside either on a PCI add-in card, or directly on a motherboard. The bridge uses data buffering and a handshaking request and acknowledge protocol to assure accurate and timely data transfer.

Abstract: A method and apparatus that enables modification of a document via telephone. One user is defined as a Driver and another user is defined as a Passenger. The Driver then determines the changes to be made to the document, and the changes are reflected in both versions of the document. Further, it is not necessary that both Driver and Passenger use the same application program.

Abstract: In a multiprocessor computer system where a number of "agents" can compete for access to a "resource", a method of ameliorating "Livelock" and preventing any such agent from being unduly frustrated from such access, this method comprising: arranging the system to include an arbitrating unit and a common system bus connecting a number of processors, plus an Avoidance unit included in each processor and including a Random-Number generator and automatic "Random Backoff" that causes an agent that fails to secure access to wait for one or more given random time periods T.sup.B before reattempting such access, with each said time period T.sup.B being provided by the random number generator so as to likely differentiate from competing agents.

Abstract: A computer system is provided comprising a first expansion bus which operates according to a first transfer protocol and adapted to couple to one or more peripheral devices. A central processing unit and a bus bridge are operatively coupled to the first expansion bus. A second bus including a second transfer protocol is coupled to the bus bridge. A plurality of peripheral devices compatible with the second transfer protocol are coupled to the second bus. The bus bridge is configured to communicate with the plurality of peripheral devices in a round-robin ping-pong fashion, wherein the bus bridge is configured to generate address/data pairs to at least one port of one of the plurality of peripheral devices, and thereafter receive address/data pairs from the at least one port of the one of the plurality of peripheral devices. The bus bridge is further configured to generate and receive address/data pairs sequentially to ports in at least a subset of the plurality of peripheral devices in a round robin fashion.

Abstract: In a multiprocessor computer system where a number of "agents" can compete for access to a "resource", a method of ameliorating "Livelock" and preventing any such agent from being unduly frustrated from such access, this method comprising: arranging the system to include an arbitrating unit and a common system bus connecting a number of processors, plus an Avoidance unit included in each processor and including a Random-Number generator and automatic "Random Backoff" that causes an agent that fails to secure access to wait for one or more given random time periods T.sub.B before reattempting such access, with each said time period T.sub.B being provided by the random number generator so as to likely differentiate from competing agents.

Abstract: A system to transfer a serial digital data protocol between a controlling processor such as digital signal processor and a plurality of analog front-end devices is described. The system has a serial clock unit to generate a serial clock reference signal, a serial data control unit to create the serial data protocol, a serial clock transmission medium, a serial data transmission medium, and an analog front-end control unit. The serial digital data protocol has a start bit time, an address time, a read/write bit time, a first high impedance time, a serial data word time, a second high impedance time, and a stop bit time. A serial data word may be transferred either from the controlling processor to the analog front-end device or from the analog front-end device to the controlling processor dependent on the state at the read write bit time.

Abstract: A commander module including means for determining whether control of a system bus is required, means for requesting control of the system bus, prior to determining whether such control is required, and means, responsive to the determining means, for indicating that control of the system bus is required. A computer system including the system bus and at least two such commander modules coupled to the system bus and including means for arbitrating for control of the system bus including means for granting control of the system bus to one of the commander modules indicating that control of the system bus is required and having the highest arbitration priority among those commander modules also indicating that control of the system bus is required.

Abstract: An improved modular solid power controller includes low cost low speed microcomputers embedded within the load cards to control a number of semiconductor power switches associated with corresponding electrical load circuits. A master controller microcomputer on the controller card communicates bilaterally with each of such slave microcomputers via a serial data path that extends along the backplane card and interconnects the former computer with each of the load cards, issuing commands in serial form and in high level language that is received by the addressed slave microprocessor, interpreted and acted upon by controlling the semiconductor power switches associated with the respective slave card.

Abstract: A computer system having suspend and resume capabilities using multiple suspend timers. The multiple suspend timers execute such that the computer system suspends after a longer period of time of user inactivity when the system is powered up in an attended mode and suspends after a shorter period of time of inactivity when the system is powered up in an unattended mode. If the system awakens in an unattended mode and user activity is subsequently detected, the system changes to suspend after the longer period of time of user inactivity. The multiple timers are implemented either by a single timer restarted to two different values or by two independent timers having different expiration values.

Abstract: In at least two microprocessor systems each having a microprocessor, a flash electrically erasable programmable read only memory (EEPROM), and a system bus connected to the microprocessor and the memory, there is disposed a controller between the system buses of the respective systems. The processor of one of the systems rewrites a program in the memory of a remaining system via the system bus of the remaining system.

Abstract: A computer system has a first bus, a first bus bridge, and a second bus bridge. The first bridge connects the first bus to a second bus and the second bridge connects the first bus to a third bus. Normally, the first bridge behaves as the only subtractive decode agent on the first bus, claiming all transactions initiated on the first bus that target agents on the second bus or the third bus. If the first bridge claims a transaction targetting an agent on the third bus, the first bridge transfers the responsibility to respond to the transaction to the second bridge. The first bridge does not behave as the subtractive decode agent on the first bus when transactions are initiated on the second bus and forwarded to the first bus. In that case, the second bridge behaves as the subtractive decode agent on the first bus.

Abstract: A shared bus non-sequential data ordering method and apparatus are provided. A maximum bus width value and a minimum transfer value are identified. A minimum number of sub-transfers is identified responsive to the identified maximum bus width value and the minimum transfer value. A bus unit having a maximum number of chips to receive and/or send data receives data in a predefined order during multiple sub-transfers. During each data sub-transfer, a corresponding predefined word is transferred to each chip of the bus unit.

Abstract: The memory card with an ECC circuit for adding ECC.sub.S to main data to be stored comprises a memory consisting of SRAM, a detection circuit for detecting the frequency of data access operation to the memory and a power supply voltage converter for lowering the power supply voltage provided from an external information processor when the frequency of data access is less than the predetermined threshold.

Abstract: A protocol for achieving atomic multicast in a parallel or distributed computing environment. The protocol guarantees concurrency atomicity with a maximum of m-1 message passes among the m server nodes of the system. Under one embodiment of the protocol, an access component message is transferred to the server nodes storing data to be accessed. The first server node of the plurality generates a token to be passed among the accessed nodes. A node can not process its request until it receives the token. A node may pass the token immediately upon ensuring that it is the current expected token.

Abstract: A system architecture is provided for configuring audio and video components connected to a computer through a textual display and a graphic display, so that users may more easily access and use all of the component capabilities of the system. Groups of related components are integrated into a comprehensive, streamlined, consistent, and coherent user interface so that the user interaction is as straightforward and consistent as possible. A component-based configuration for the connected components permits new components to be easily added.