Abstract: When a first bus master device issues a bus request on a first request signal line, a centralized arbitration circuit in a system bus manage circuit issues a bus grant signal on a first grant signal line if the bus is available for use. This causes the first bus master device having gained the ownership of the bus to issue a read request to a first slave device. At this time a first signal line is designated. Even before the sending of the read data constituting a response to this read request to the first bus master device, a bus request from a second bus master device can be accepted if the data bus is unoccupied. Thus, the centralized arbitration circuit in the system bus manage circuit issues a grant signal on a second grant signal line. This causes the second bus master device having gained the ownership of the bus to designate a second end signal line, and to issue a read request to a second slave device.

Abstract: A system is disclosed for optimizing data transfer times between an external Master device and main memory. The system includes an integrated processor with a PCI bridge for orchestrating data transfers with the PCI Master over the PCI bus, and a memory controller for controlling access to the main memory. During burst cycles of the PCI Master, the PCI bridge expedites data transfers by providing the memory address to the memory controller early during periods when the PCI Master is slow in transmitting or receiving data. When the PCI Master is unable to respond in a timely fashion, and while the PCI bridge is in control of the local bus, the PCI bridge asserts a MEMWAIT signal to the memory controller to indicate the need to throttle down a data transfer.

Abstract: The present invention provides an "alert" interface for a component which can be safely "hot-plugged/unplugged" to an "alert" interconnect of an electrically powered system. The alert interface has a mating edge which includes daughter precharge/ground connectors, a daughter (engage) waning connector, a number of daughter signal connectors and a daughter engage connector. The alert interconnect includes corresponding mother connectors. The respective connectors of the interconnect and the interface are arranged so that they mate in the following exemplary order when the interface is hot-plugged/unplugged to the interconnect: precharge/ground connectors, warning connectors, signal connectors and finally engage connectors. When the daughter (engage) warning connector mates with the mother warning connector, the component sends an "engage warning" signal to the powered system.

Abstract: A system for handling multiple nested interrupts in a microprocessor device using C language interrupt handlers in which each interrupt handier is executed in two distinct stages, which are a Freeze mode handler and a signal handler, is disclosed. Upon the occurrence of each interrupt, a microprocessor of the device is placed in Freeze mode and the appropriate Freeze mode handler responds immediately to the interrupt, capturing all critical data and deactivating the interrupt request. Once the Freeze mode handler has completed execution, if execution of the signal handler is not necessary, an "interrupt return" or "IRET" instruction is executed, causing execution to return to the point at which the interrupt occurred. Otherwise, a signal number of the appropriate signal handler is pushed onto a signal stack stored in a memory associated with the microprocessor and a determination is made as to whether the signal dispatcher is running.

Abstract: A personal computer (PC) card insertion method and apparatus uses a subset of connector ground terminals and pins, located at either end of the connector, for detecting the onset of a card insertion. The host PC card slot connector has pull-up resistors for keeping the subset of ground terminals at a high logic level (V.sub.CC). Also, the subset of pins are made longer than the signal pins so that when an insertion of a PC card begins, the grounding of one or more of the subset of pins indicates that a PC card insertion has begun, allowing the host system to take the necessary precautions to ensure an orderly acceptance of the card without any undesirable system affects that might otherwise result. Also, a logic network for using the subset of connector terminals as additional grounding connections is provided upon completion of the insertion.

Abstract: A structure and method for using variable length instructions in an instruction register having a fixed word boundary. The instruction register accommodates a first word and a second word. The first word has a first base instruction and a first flexible instruction aligned with first and second predetermined positions, respectively, in the instruction register. The second word has a second base instruction and a second flexible instruction aligned with third and fourth predetermined positions, respectively, in the instruction register. The first and second base instructions and the first and second flexible instructions each have a fixed length. The first base instruction can (1) stand alone as an independent instruction, (2) be combined with the first flexible instruction to form a once-extended instruction, or (3) be combined with the first and second flexible instructions to form a twice-extended instruction.

Abstract: Processing of an asynchronous signal directed to a thread comprising a software routine executing in a computer system such that data consistency is maintained is discussed. Such processing proceeds by determining whether the routine is signal safe such that processing of the routine may be interrupted in order to process the signal without possibly causing inconsistency of data. The routine is asynchronously interrupted and the signal is processed immediately if the routine is signal safe. If the routine is not signal safe, then the routine is not asynchronously interrupted and processing of the signal is deferred to a time when the signal may be processed without possibly causing inconsistency of data.

Abstract: A method and apparatus for reducing the power consumption of a processor in a computer system where a programming structure running on the processor determines when the processor is in an inactive state to cause clocking signals and the power supply to be disabled to the processor. The processor is again coupled to the power supply and the clock signals in response to a periodic interrupt signal, a non-periodic interrupt or a bus request from a peripheral device. Thereafter, the programming structure signals the control logic again when the processor reenters the inactive state, such that the control logic disables the clock signals and decouples the power supply to the processor when the processor returns to the inactive state. The method is extended to offer the ability to shut down the processor from programming structures running on alternate masters or subsystem controllers within the same system.

Abstract: A hardware device known as a RICH coupler which works between an IC card and its corresponding terminal system. The function of the RICH coupler depends upon its position. Between the card level and the system level there is a third independent level, the coupler. The card level and the system level are involved in the specific card application. The coupler level is application independent. The present invention provides an application independent RICH coupler which works like a supervisor between the applications on the card level and the applications on the system level.

Abstract: A method of state splitting in a state machine includes determining a number N of logic levels, i.e. CLB levels, for each state in a state machine. Number N is equal to N.sub.i-1 +log.sub.k f.sub.i wherein "k" is the number of input lines to a CLB, "i" is a particular node in a particular hierarchial level in the Boolean logic, and "f" is the number of fanin transitions to the particular node. An average number N(AV) as well as a maximum number N(MAX) of CLBs to implement the states in the state machine are also determined. Then, predetermined exit criteria are checked. One exit criterion includes determining that the maximum number N(MAX) is not associated with a state register, but is instead associated with an output, for example. Another exit criterion includes providing a ratio by dividing the maximum number N(MAX) by the average number N(AV). If the ratio is less than or equal to a split-factor, then this exit criterion is met. In one embodiment, the split factor is between 1.5 and 2.0.

Abstract: A parallel computer network wherein an arbitration circuit for performing arbitrating operation over a plurality of processing requests at the same time at high speed is provided in a crossbar network control circuit to thereby prevent the processing requests not selected from being kept awaited for a long time. The arbitration circuit includes a priority bit change circuit which has a plurality of adders for adding a preset value to the priority information of the each awaited processing request and also has a plurality of comparators for detecting the requests being awaited.

Abstract: Postponing the interrupt for an I/O event can increase system throughput by amortizing the cost of the interrupt service routine over multiple I/O events. In current systems that provide interrupt postponement, the time parameter is fixed. Fixed values can lead to parameter configuration errors, excessive characterization work to generate parameter values, and a failure to automatically re-configure to system changes or to external load changes. The proposed mechanism measures actual system experience and eliminates the parameter configuration effort by filtering its own experience to derive a target value for interrupt postponement. A current postponement value with the potentially greater variance than the target is used to rapidly respond to abrupt change in offered load. The invention also benefits tasks with real-time deadlines to provide correct system operation.

Abstract: Microcode is loaded into, for example, a processor or I/O module within a computer system without manually halting and restarting the computer system. In other words, microcode can be loaded into the computer system dynamically while data processing continues from the processor or I/O module states just prior to the microcode load with no major interruption to the user. A microcode image is loaded into a processor which is already executing one or more tasks. A request to load microcode into the processor is received. The processor is signalled to suspend task execution. After the microcode image is transferred into the processor, the processor is signalled to resume task execution.

Abstract: A system and method for processing data storage mediums (DSMs) that are not stored in an automated data storage library on medium drive devices that are part of the library. An input station used to add DSMs is enabled to serve as an input and output window for transient data storage mediums (TDSMs) so that DSMs are not dislodged from the storage bins. An operator may automatically place the library's robotic picker in a "TDSM mount mode" when an attached host processor requests one or more data volumes stored on one or more TDSMs. A library-manager controller can be automatically configured to interact with the library's robotic pickers to transfer a TDSM from the input/output station to a device, such as a tape drive within the library. The library manager controller is automatically configured to ignore the machine readable external label of a TDSM so that it is not necessary to place such a label on a TDSM.

Abstract: Techniques for controlling a process which is performed at least in part by a device such as a computer operating system. The techniques involve a process server which controls the process in response to indications that steps of the process have taken place, an envelope which encloses the device and generates event messages when the device performs operations, and a translator which translates steps of the process into sequences of events and monitors the event messages. When the translator determines that a sequence of events which constitute a process step has occurred, it provides an indication that the step has occurred to the process server. In a preferred embodiment, the device is an operating system, the envelope is a dynamically-linked library of file system commands, the translator includes the Yeast event-action system, and the process server is a process control system which models entities involved in the process as objects and makes state transitions by firing rules which modify the objects.

Abstract: A direct memory access (DMA) controller having a first mode and a second mode controls communication between a module bus, communicating with a processor and a memory, and an input/output (I/O) bus communicating with an external device. A data controller subsystem stores I/O bus input data to provide module bus output data, and stores module bus input data to provide I/O bus output data. A device address controller subsystem stores a device address from the module bus to provide an I/O device output address to the I/O bus for addressing the external device. A memory addressing subsystem receives module bus input data to form an initial memory address provided to the module bus representing a storage location in the memory. An incrementer increments the initial memory address.

Abstract: An information processing system wherein a module to operate as a master which executes a read access to a module to operate as a slave requests a bus arbiter to afford the mastership of a bus with a bus mastership request signal, and it simultaneously asserts a last cycle signal so as to notify the bus arbiter of the fact that the next cycle will be the last cycle to be used by the master. Subsequently, when the master has had the use of the bus granted by a bus use grant signal from the bus arbiter, it transfers an address to the slave by the use of the bus in the next cycle, thereby starting the read access. After the read access, the master releases the bus mastership. Only when the slave has failed to accept the transferred address, does it assert a retry request signal two cycles after the transfer cycle of the address not accepted. In this case, the module having executed the transfer two cycles before the cycle of the asserted signal executes again the transfer executed before.

Abstract: A flat panel display power management system for a flat panel display screen in a portable electronic device is disclosed. The flat panel display power management system is capable of controlling the amount of power delivered to each pixel on the flat panel display screen. The portable electronic device can select a subset of important pixels that will continue to receive more power than the remaining pixels if the flat panel display power management system enters a reduced power mode. When the electronic device system determines that the user has been inactive for a predetermined amount of time or if the user manually requests low power mode, the flat panel display power management system enters the reduced power mode. In the reduced power mode, the flat panel display power management system reduces the power provided to the pixels that are not within the subset of important pixels.

Abstract: The computer system includes an integrated processor coupled to a power management unit and at least one peripheral device. The integrated processor includes a bus interface unit that provides an interface to a high performance peripheral interconnect bus with multiplexed address/data lines. The peripheral interconnect bus, which may be a PCI standard bus, accommodates data transfers between an internal bus of the integrated processor and PCI peripheral devices. The integrated processor further includes a sub-bus control unit that generates a set of side-band control signals that allow the external derivation of a lower performance secondary bus, such as an ISA bus, without requiring a complete set of external pins for the secondary bus on the integrated processor. The derivation of the secondary bus is accomplished with an external data buffer and an external address latch which are controlled by the side-band control signals.

Abstract: A computer system that contains devices and peripherals that have power management capabilities incorporated therein that are responsible for placing the computer system in a reduced power consumption state. A controller monitors bus cycles from a processor. Upon the completion of each bus cycle, the controller provides a completion indication to the processor. In the present invention, the controller withholds the completion indication for a period of time after completion of each of the selected bus cycles to control power consumption by the processor, thereby extending the time in which the processor is in the reduced power consumption state. In this way, power consumption in the processor is controlled within an instruction boundary.