Abstract: Bus interfaces for nodes coupled to a system bus in a computer system, the system bus including an address bus and a separate data bus. System bus operations include address and command transactions and data transactions. Data transactions occur on the data bus separately and independently of the occurrence of address and command transactions on the address bus. A bus interface may include any of a commander address bus interface means for providing to an address bus address and command transactions, a responder address bus interface means for acknowledging receipt of address and command transactions via the address bus, a commander data bus interface means for controlling submission to the data bus of data transactions as a result of the occurrence of address and command transactions on the address bus, and a responder data bus interface means for transferring data on the data bus during a data transaction.

Abstract: Rush current is dispersed with a power control section having a simple construction, irrespective of the number of disk units. A plurality of disk modules each having a built-in power section and a built-in disk drive are grouped and housed in a single disk unit. A plurality of disk units are provided in response to the system scale. An input/output control section is provided in a disk unit, and performs control of data input/output to and from the plurality of disk modules in the same unit and issuance, upon power-on, of a power-on instruction in compliance with a predetermined procedure. There is provided a first power control section common to all the disk units for instructing power-on in a lump.

Abstract: A wait state mechanism for lengthening a microprocessor's bus cycle to allow data transfers between slower off-chip devices. A microprocessor is responsive to a bus control signal generated by external programmable logic which instructs the microprocessor to insert wait states of varying number depending on the component involved in a bus transaction. The microprocessor receives only a single input from the programmable logic and varies its bus cycle length accordingly.

Abstract: Arbitration means for arbitrating between computer devices A to F which compete for access to a common bus. The system provides cascaded round-robin units. Unit RR1 has ports A, B, C, and X in sequence, with port X coupled to round-robin unit RR2, which has ports D, E, F in sequence. On each cycling of unit RR1 past C to A, unit RR2 is checked and the next one of devices D to F (in the sequence determined by unit RR2) has the opportunity of bus access. A gating circuit 13 can further restrict bus accessing by unit RR2's devices, by timing or counter control. A third round-robin unit can be added coupled to unit RR1 (which would have ports A, B, C, X,Y) or to unit RR2 (which would have ports D, E, F, Y). The assignment of devices to ports can be controllable by a matrix switch and device assignment memory.

Abstract: A microcomputer includes a data processor in a bus transfer circuit of the microcomputer and, therefore, simple data processing is enabled when data are transferred to a bus. Further, a microcomputer includes a bit shifter that shifts the data to an upper bit direction or to a lower bit direction while transferring the data to a bus from a memory and, therefore, bit shifting processing, which is a light load, is enabled while transferring data from the memory to a bus. Further, a microcomputer includes a bit processor that performs an operation on an arbitrary bit of data while transferring the data to a bus from the memory and, therefore, bit processing, which is a light load, is enabled while transferring data to a bus from the memory. Furthermore, a microcomputer includes a bit reverser that inverts the positions of bits in a bit sequence and, therefore, bit reversing processing, which is a light load, is enabled.

Abstract: A method for transferring data in a controller having a processor and a controller support device, with the controller connected to a host device and a disk drive. The method includes the steps of providing the controller with a first bus and a second bus, connecting a first bus between the disk drive and the host device, connecting a second bus between the processor and the controller support device, transferring first data between the disk drive and the host device across the first bus, and transferring second data between the processor and the controller support device across the second bus without consuming any portion of the bandwidth of the first bus. A controller architecture is also disclosed.

Abstract: A method and apparatus for determining the status of a resource shared by multiple subsystems operating in mutually asynchronous clock domains apply a one-bit counter for each subsystem and synchronize the value of each such bit counter with all asynchronous clocks. Each subsystem exclusive-ORs the value of each bit counter to generate an availability status for the shared resource. System delays caused by synchronization are minimized, and circuit design and proof of correctness at the design stage are simplified.

Abstract: A flash electrically-erasable programmable read only memory (EEPROM) array and a method for allowing a host computer to detect a plurality of different power-expending modes into which a storage device may be placed for operation, to select a particular one of those modes to match the power abilities of the host computer, and then to place the storage device in the proper power mode of operation to best function with the host system.

Abstract: An information processing system has a plurality of information processing units. Each information processing unit has a system console interface control unit (SCI) connected to an information processing unit body (COM) and a service processor (SVP). The plurality of system console interface control units (SCI) are connected each other in a ring fashion. Each system console interface control unit (SCI) has a processing devcice for processing an interface between the self-service processor (SVP0) and the other-information processing unit body (COM1).

Abstract: An intelligent power strip circuit for providing automatic computer system power down features and for providing automatic restoration of power for the computer system. The intelligent power strip circuit may be used by conventional computer systems that do not have internal power management features to retrofit them to provide power conservation modes. The circuit is responsive to an incoming phone call and will provide automatic power on and system initialization to enable the computer system to respond to a call. The circuit is responsive to the keyboard, mouse, and other user interface devices (for automatic power up and conditional timed power off) because these devices are routed through the external circuit to the computer system. Peripherals and the CPU chassis of the computer system receive their AC power via the circuit and therefore may be automatically powered down under control of the CPU when appropriate.

Abstract: A computer system including a central processing unit (CPU) and a power management circuit (PMC). The CPU has an active mode where it is responsive to interrupt and direct memory access requests, and a standby mode where it is in a low power state and is not responsive to the interrupts and direct memory access requests. The PMC monitors the interrupts and direct memory access requests in the system when the CPU is in the standby mode, and causes the CPU to enter the active mode upon the detection of either an interrupt or a direct memory access request.

Abstract: A method and apparatus for sensing the state of a computer system and changing the state, if necessary, before connecting the computer system to a computer expansion unit. The computer system has an electrical sense pad on which it sets a state signal. This state signal can indicate one of several states of the computer system. When the computer system is placed in the computer expansion unit, the expansion unit detects the state signal from the electrical sense pad and determines the state of the computer therefrom. If the determined state is an acceptable state, then the expansion unit will complete the connection of the computer to itself. If the determined state is an unacceptable state, then the expansion unit will delay completion of the connection and will send a signal back to the computer system telling the computer system to change its state.

Abstract: An electronic system (6) has a power management logic circuit (920). A first power supply connector (1902) is electrically coupled to the power management logic circuit (920) and a second power supply connector (1904) is also electrically coupled to the power management logic circuit (920). The power management logic circuit (920) has a first logic section (920A) connected to the first power supply connector (1902), and the first logic section (920A) has a suspend output (SUSPEND#). A second logic section (920B) is connected to the second power supply connector (1904) for operation independent of the first logic section (920A) when power is available at the second power supply connector (1904, RTCPWR) and suspended at the first power supply connector (1902, VCC).

Abstract: A digital rheostat or potentiometer which provides both increment and decrement operations from a single input such as a pushbutton. A certain pattern of input actuations will cause the direction of change to reverse. Settings of the potentiometer are stored in nonvolatile memory.

Abstract: A last power state apparatus including a power supply controller having a battery-backed memory bit for retaining the power state of an electronic device during a failure of a primary power source. The battery is preferably a lithium type battery and the power supply preferably provides a flea power signal when primary power is available to maintain the state of the memory bit even if the power supply is off. The controller asserts a power status signal to the power supply based on the state of the memory bit, so that the power supply remains off or powers up as appropriate when primary power is next available. A momentary power switch is used to manually turn on and off the power supply and the electronic device by toggling the memory bit. The electronic device, which is typically a computer system, provides signals to the power supply controller to turn off the device. Further, the computer can enable an interrupt to prevent the user from turning off the device until after vital functions are completed.

Abstract: A data-storage and processing card has a data-storage memory and a read/write memory. Data processing instructions are stored in the data-storage memory, along with the data. The data processing instructions require memory storage capacity for their execution, and the read/write memory is selected to be sufficiently large to meet this processing storage capacity requirement. To process the data, the card is plugged into a host computer, whose central processing unit recalls and executes the processing instructions. The read/write memory of the card is utilized as the required memory storage capacity for the processing. Alternatively, the card may include a central processing unit that processes the instructions. The card is particularly useful for storage of data compressed form and decompressing the data with data decompression processing instructions.

Abstract: A multi-processing software system (200) has multiple operating processes (221, 222, 223, 224, 225, 226, 227, 228) that communicate with each other using messages. Each process has a corresponding process class (410, 411, 412, 413). Each message is assigned a message type (450, 451, 452, 453), and messages types are mapped (400) to least one process class. A particular message is routed to processes having a process class corresponding to the one or more process classes mapped to the message type of the particular message.

Abstract: A method and apparatus for providing a plurality of digital devices, including protocol analyzers, work stations, cable testers, and the like, with a data signal received from one of a plurality of target networks is. A plurality of data ports, including at least one target data port, a plurality of device data ports, and a plurality of intermediate data ports. Data channels establish a plurality of device data paths between a plurality of digital devices and a corresponding plurality of device data ports and a target data path between one of the target networks and at least one of the target data ports. A switch establishes a first data path between any selected one of the plurality of target data ports and a respective first intermediate data port. A replicator replicates a first data signal from the first intermediate data port at least to a second intermediate data port and to a third intermediate data port.

Abstract: A bus interface system and method for communication between different computer components having buses with different speeds, data widths, or protocols. A first state machine communicates with the first bus and a second state machine communicates with the second bus. Each of the buses communicates with a data storage device. The first and second state machines are in selective communication using an asynchronous handshaking protocol, whereby data is transferred between said first and second buses. The handshaking protocol comprises an asynchronous request signal from the first bus requesting a data transfer and an asynchronous reply signal from the second bus indicating that data has been sent or is available.

Abstract: A method and system for operating a computer system in a low power mode in which the central processor unit (CPU) responds only to system events that require CPU operation is described. The invention inclues providing register banks on system logic coupled to the CPU which determines whether interrupt signals generated on the system require CPU attention and the priority to be accorded to the processes associated with the interrupt signals.