Abstract: A computer system that is able to specify a packet size transmission rate is disclosed. The computer system has a plurality of nodes, each node being serially connected on a P1394 bus to at least one other node in the computer system. The nodes communicate one to another by transmitting communication packets having variable byte sizes over the P1394 bus. The packet size transmission rate is specified by first establishing an average transmission of bytes per packet. Next, the system determines an approximate value of the average transmission rate and, based on this value, determines a periodic change on the average transmission rate for transmitting communication packets of length l or length l+1. Once the periodic change is understood, the system selects a repeating pattern for generating a sequence of packets representing this approximate value. This sequence allows for an even transmission distribution of l and l+1 packets.

Abstract: A data replacing unit replaces a data packet among a plurality of predetermined data packets in the data replacement manner, which manner is provided by a first control unit as is necessary. An initializing unit generates initializing data using a high-speed clock, clock speed of which is higher than that used by the first control unit, the initializing data being used for initializing the data replacing unit so as to refresh the replacing unit before the data replacement operation is started. A selecting unit, initially and until the initialization is completed, selects data so that the initializing data is provided to the data replacing unit but the control data is not provided thereto.

Abstract: A method of communicating with peripheral devices via a personal computer parallel port having computer data bus lines but no address bus lines comprising connecting the input of a multiplexer to the parallel port, the multiplexer having a data bus input and a databus output and an address bus output, applying address data to the computer data bus, applying an address control signal to the multiplexer and passing the address data only to the address bus output as a result thereof.

Abstract: A multipoint data collection system uses multiple parallel data buses connecting a central controller to addressable sensor interfaces to permit any sensor to be connected to a central controller over any one of the data buses. Both ends of each data bus are connected to the central controller, allowing sensor interfaces to be addressed even if all data buses are cut. Faults on a data bus and defective sensor interfaces may be bypassed through one or more bypass buses that may be addressably switched into use as desired.

Abstract: Expansion registers E0 to E7 are added to the existing general registers R0 to R7 built on-chip in an 8-bit CPU (1) so that all the registers including the added expansion registers may be grasped in its entirety as address data to access to a memory or the like. The address operation is executed at a unit including both the expansion register and the corresponding general register. All the registers including the expansion registers are grasped as one unit of address data to handle the carry or borrow caused in the address operation. Since the expansion registers have their applications limited to the generation of address, the number of kinds or combinations of executable instructions is reduced without inviting a serious reduction in the data processing ability thereby to suppress the increase in the logical and physical scales of the CPU. The register is given 32 bits in its entirety by adding the expansion register Ei of 16 bits to the general registers RiH and RiL of 16 bits of the 8-bit CPU.

Abstract: A method and system for determining the maximum number of cable segments between all possible node to node paths on a high performance serial bus. The method for determining the maximum cable hops on the serial bus, which is acyclic and based upon the IEEE 1994 standard, consists of traversing a direct path between two nodes via the parent links. Further, the number of traversed paths is reduced from all possible node-to-node paths to only leaf-to-leaf node paths and leaf-to-root node paths for efficiently identifying the maximum number of cable segments between any two nodes within the serial bus.

Abstract: The technical field of the invention generally concerns digital computers and, in particular, repeaters or switches (40) for distributed arbitration digital data buses (52, 54, 56, and 58) to which devices (62, 64, 66, 68, 72 and 74) connect in parallel. The bus repeater/switch (40) includes a plurality of bus interface cards (48) that are connected to the distributed arbitration buses (52, 54, 56 and 58) for receiving signals from and transmitting signals to devices (62, 64, 66, 68, 72 and 74) connected thereto. The bus interface cards (48) connect to a control card (44) which allows signals from one of the sharing buses (52, 54 or 56) to be exchanged with the shared bus (58). The bus switch (40) also includes selector switch (84 or 88) for choosing which particular one of the sharing buses (52, 54 or 56) exchanges digital data signals with the shared bus (58).

Abstract: An electronic system (100) includes a first integrated circuit (IC) (112) having a card system management interrupt (SMI) output pin (CRDSMI#) and interrupt pins (IRQ3-5), and a logic circuit (1620, 1630) having an output connected to the card SMI pin. This logic circuit further has inputs connected to a first and second set of registers and logic for first and second cards (CARD A,B) respectively. Each of the first and second sets of registers and logic include a first register (CSC REG) having bits set by at least a card event (CDCHG) and a battery condition event (BWARN) respectively. A logic gate (2672) responds to combine the bits from the first register. A second register (INT AND GEN CTRL REG) has a bit (SMIEN) for steering the output of the logic gate (2672) for ordinary interrupt or for system management interrupt purposes depending on the state of the bit (SMIEN).

Abstract: Hardware input/output address translation apparatus adapted for use in a multitasking computer system including hardware responsive to commands from an unprivileged application program addressed to an input/output address for translating the input/output address to a physical address space of an input/output device and transferring the command to the physical address of an input/output device, hardware responsive to commands from an unprivileged application program addressed to an input/output address for selecting from safe translations of input/output addresses to physical address spaces of input/output devices for the first hardware means, and apparatus for handling a failure to provide an address translation.

Abstract: In a portable electronic device, a method and apparatus for providing a predetermined portion of a limited resource from a programmable resource allocators (PRAs) (240) to a processor (22) to execute a task (210) optimally. The processor (22) programming the PRA with a resource utilization input (RUI) (250) prior to executing the task (210). The RUI (250) stored in a task descriptor (220), and the task descriptor (220) and the task (210) stored in the memory (200).

Abstract: A magnetic disk apparatus which is used as a subsystem of a computer system, in particular a medium-sized computer system which uses commercial power and does not have its own backup power, provided with a plurality of directors (118), a plurality of magnetic disk modules (148) commonly accessed from the plurality of directors, a plurality of director batteries (114-m) for supplying power individually to the plurality of directors, magnetic disk module batteries (114-n) for supplying power to the magnetic disk modules, and a power controller (110) for independently controlling the supply of power from the plurality of director batteries and magnetic disk module batteries in accordance with the operating state of the plurality of directors and magnetic disk modules. (FIG. 1).

Abstract: A low power, single master, variable clock rate, daisy-chainable, serial bus connects a bus dispatch in a base station (master) to a chain of one or more daisy-chained peripheral devices (slaves). The bus has a bidirectional serial data line, a bidirectional clock line, unidirectional interrupt line, power and ground lines. Data and commands are sent from the base station to a peripheral device, and data is received from the peripheral device by the base station by configuring each peripheral device on the bus to receive data and clock signals from the base station in an idle mode of operation. Upon a command send being transmitted by the base station, all peripheral devices on the serial bus between the base station and an addressed peripheral device remain in the idle mode and the addressed peripheral device is connected to the bus so that clock and data signals on the bus to are passed to the peripheral device.

Abstract: An apparatus for configuring multiple agents in a computer system includes a first storage device for storing a set of configuration values and a second storage device for capturing the set of configuration values from the bus. These configuration values are driven onto the bus and retrieved from the bus by interface logic within the apparatus. The interface logic drives the configuration values onto the bus when a register within the apparatus is activated. At system power-on, the first storage device defaults to a first set of values. These values are then driven onto the bus and retrieved by each agent on the bus, including the apparatus of the present invention. This first set of values provides the system with the necessary parameters to access and execute certain initialization program(s). These initialization programs can modify the configuration values stored in the first storage device.

Abstract: A system and method which utilizes a unique bus protocol in conjunctions plural Dval.sub.-- control signals to minimize the dead time between blocks of data being transferred between components is a data processing system. The present invention introduces another latch-to-latch data valid control signal and alternates the usage of this signal during back to back data transfers from the same or different bus devices. In this manner the restore and tristate dead cycles are totally overlapped with the data transfer and the minimum possible number of dead cycle(s) is achieved between different blocks of data transfers. With the method of the present invention, data providers alternately activate the Dval.sub.-- signals and data receivers look at all Dval.sub.-- signals and if any one of them is active, then the data is considered valid and can be read.

Abstract: A number of new interrupts, interrupt handlers, digital signal processing (DSP) tasks, registers and FIFOs are provided to an add-on fax/modem card and its host processor. The new FIFOs are used to facilitate rerouting of the transmit and receive data to the host for processing by the DSP task while maintaining compatibility, thereby off loading the add-on fax/modem card. The new interrupts and interrupt handling functions are used to facilitate the data rerouting, redirecting execution control between the host and the on-board processors with minimal latency. The new registers are used to facilitate the execution control redirection, transferring control and status information between the host and the on-board processors.

Abstract: A CPU has an upper compatibility with a low-order CPU to expand a continuously usable address space relatively. For latching data information, registers are constructed for being an address register with a bit number larger than the address bit number of a low-order CPU. The data information has its byte/word size specified by the size bit of an operation code. The utilization of the data information of a long word size is specified by either the prefix code or the operation code to which is newly added the same bit number as that of the low-order CPU. For the data information of the byte size, the high-/low-orders of the byte size register to be utilized are specified by predetermined 1 bit of a register specifying field. For the data information of the word size, the high-/low-orders of the word size register are specified by the predetermined 1 bit of that data information.

Abstract: A buffer circuit for transferring data between a first slower narrower computer bus and a second wider faster computer bus which buffer circuit includes first and second buffers each capable of storing a plurality of bytes of data equivalent to the width of the second bus, a single address register for holding an address which represents data in either of the two buffers, the lowest order bit of the address register indicating to which one of the two buffers data is being written, first and second registers for storing indications of valid data in the first and second buffers, and a control circuit for controlling the filling of the first and the second buffers in accordance with the byte addresses furnished and the flushing of the first and the second buffers whenever a most significant byte of a buffer has valid data, whenever an attempt is made to write to a buffer address containing valid data, and whenever an attempt is made to load data to a buffer address different than an address in the address regist

Abstract: An information processing system wherein a module to operate as a master which executes a read access to a module to operate as a slave requests a bus arbiter to afford the mastership of a bus with a bus mastership request signal, and it simultaneously asserts a last cycle signal so as to notify the bus arbiter of the fact that the next cycle will be the last cycle to be used by the master. Subsequently, when the master has had the use of the bus granted by a bus use grant signal from the bus arbiter, it transfers an address to the slave by the use of the bus in the next cycle, thereby starting the read access. After the read access, the master releases the bus mastership. Only when the slave has failed to accept the transferred address, does it assert a retry request signal two cycles after the transfer cycle of the address not accepted. In this case, the module having executed the transfer two cycles before the cycle of the asserted signal executes again the transfer executed before.

Abstract: A non-volatile semiconductor memory device includes a memory cell array including a plurality of memory cells, an address latch circuit supplied with address for latching the same, a data latch circuit supplied with data for latching the same, a sense amplifier for amplifying data read out from the memory cell array, a write control circuit for controlling write operation, a register for holding a predetermined data, and a selection circuit supplied with a busy signal from the write control circuit indicating that the semiconductor memory device is operating in a writing mode for writing data into the memory cell array, for selecting one of an output signal of the sense amplifier and an output signal of the register in response to the busy signal.

Abstract: A computer system having a responsive low-power mode and a full-power mode of operation. The computer system includes a power consumption controller, a processor and a communication device. The power consumption controller generates an interrupt signal in response to a low power event or a fully operational event. The power consumption controller also generates a clock control signal. The clock control signal is deasserted during the full-power mode of operation and alternatively asserted for a first duration and deasserted for a second duration during the low-power mode of operation. In response to an asserted clock control signal, the processor suppresses the internal clock signal to at least one functional block within the processor and in response to a deasserted clock control signal, the processor transmits the internal clock signal to at least one functional block within the processor.